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Difference between revisions of "amd/microarchitectures/k10"
| Line 9: | Line 9: | ||
| process = 65 nm | | process = 65 nm | ||
| process 2 = 45 nm | | process 2 = 45 nm | ||
| − | + | |isa=x86-16 | |
| + | |isa 2=x86-32 | ||
| + | |isa 3=x86-64 | ||
| succession = Yes | | succession = Yes | ||
| predecessor = K8 | | predecessor = K8 | ||
Revision as of 12:59, 30 November 2017
| Edit Values | |
| K10 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | AMD |
| Introduction | November 11, 2007 |
| Process | 65 nm, 45 nm |
| Instructions | |
| ISA | x86-16, x86-32, x86-64 |
| Succession | |
K10 (sometimes 10h) was the microarchitecture developed by AMD as a successor to K8. K10 was superseded by Bulldozer in 2011.
Architecture
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This section is empty; you can help add the missing info by editing this page. |
Die Shot
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This section is empty; you can help add the missing info by editing this page. |
All K10 Chips
| K10 Chips | ||||||
|---|---|---|---|---|---|---|
| Model | Family | Core | Launched | Power Dissipation | Freq | Max Mem |
| Count: 0 | ||||||
See also
Facts about "K10 - Microarchitectures - AMD"
| codename | K10 + |
| designer | AMD + |
| first launched | November 11, 2007 + |
| full page name | amd/microarchitectures/k10 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-16 +, x86-32 + and x86-64 + |
| manufacturer | AMD + |
| microarchitecture type | CPU + |
| name | K10 + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) + |