Semiconductor & Computer Engineering
| Line 22: | Line 22: | ||
|package module 1={{packages/bitmain/fcbga-1599}} | |package module 1={{packages/bitmain/fcbga-1599}} | ||
}} | }} | ||
| − | '''Sophon BM1680''' is a [[neural processor]] designed by [[Bitmain]] and introduced in 2017. The BM1680 is capable of performing both network inference and network training. | + | '''Sophon BM1680''' is a [[neural processor]] designed by [[Bitmain]] and introduced in 2017. The BM1680 is capable of performing both network inference and network training. Capable of delivering up to 2 TFLOPS (SP), the BM1680 has a typical power dissipation of 25 W with a peak power of 41 W. The chip was [[taped-out]] in April 2017 and began sampling in June. |
Manufactured on [[TSMC]]'s [[28 nm|28HPC+]] process, the BM1680 is capable of 80 billion algorithmic operations per second. Bitmain claims the chip is designed not only for inference, but also for training of neural networks, suitable for working with the common [[artificial neural network|ANNs]] such as [[convolutional neural network|CNN]], [[recurrent neural network|RNN]], and [[deep neural network|DNN]]. | Manufactured on [[TSMC]]'s [[28 nm|28HPC+]] process, the BM1680 is capable of 80 billion algorithmic operations per second. Bitmain claims the chip is designed not only for inference, but also for training of neural networks, suitable for working with the common [[artificial neural network|ANNs]] such as [[convolutional neural network|CNN]], [[recurrent neural network|RNN]], and [[deep neural network|DNN]]. | ||
| Line 30: | Line 30: | ||
:[[File:BM1680 block diagram.png|650px]] | :[[File:BM1680 block diagram.png|650px]] | ||
| + | |||
| + | |||
| + | === BMDNN Chiplink === | ||
| + | The chip incorporates Bitmain's proprietary fabric called ''BMDNN Chiplink technology''. The [[fabric]] is a flexible, low latency link that communicates over a high-speed [[SerDes]] PHY. Two ports are available on each chip which allows multiple BM1680s to be daisy chained together to form a larger network. | ||
| + | |||
| + | In a typical configuration (i.e., a PCIe [[accelerator]] [[accelerator card|card]]), two BM1680s chips are wired together using chiplink. The first node in the chain is then connected to a host control (e.g., a custom [[ASIC]] unit or simply an [[FPGA]]) which provides a PCIe interface to the host processor (e.g., on a typical server a {{intel|Xeon}}). Data from the host processor is then sent to the host controller on the accelerator unit which is then distributed across all the [[NPU]]s on all the available nodes. | ||
| + | |||
| + | ::[[File:BM1680 chiplink topology.png|450px]] | ||
| + | |||
| + | Current offering by [[Bitmain]] is limited to two BM1680s chips per [[accelerator card]], however in theory the chip can be chained to form a much larger network. The primary limitations of the network are power consumption and thermal dissipation as well as PCIe bandwidth which Bitmain requires to be x4 lanes per node (or 3.9 GB/s, 8 GT/s). For example, current offerings by Bitmain features two nodes on a PCIe Gen3 x8 card. | ||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=DDR4-2666 | ||
| + | |ecc=Yes | ||
| + | |max mem=16 GiB | ||
| + | |controllers=1 | ||
| + | |channels=4 | ||
| + | |max bandwidth=79.47 GiB/s | ||
| + | |bandwidth schan=19.87 GiB/s | ||
| + | |bandwidth dchan=39.74 GiB/s | ||
| + | |bandwidth qchan=79.47 GiB/s | ||
| + | }} | ||
Revision as of 16:58, 18 November 2017
Template:mpu Sophon BM1680 is a neural processor designed by Bitmain and introduced in 2017. The BM1680 is capable of performing both network inference and network training. Capable of delivering up to 2 TFLOPS (SP), the BM1680 has a typical power dissipation of 25 W with a peak power of 41 W. The chip was taped-out in April 2017 and began sampling in June.
Manufactured on TSMC's 28HPC+ process, the BM1680 is capable of 80 billion algorithmic operations per second. Bitmain claims the chip is designed not only for inference, but also for training of neural networks, suitable for working with the common ANNs such as CNN, RNN, and DNN.
Overview
The chip consists of five subsystems: NPU, MCU, Chip Link, Memory, and Peripherals. The MCU Subsystem is a low-power embedded ARM microcontroller. The NPU Subsystem consists of 64 NPUs, the hub, and an NPU Schedule Engine. The scheduling engine is in charge of controlling the data flow to the individual NPUs. Bitmain has not many intimate details of the NPU cores but each core is known to have 512 KiB of program-visible SRAM and supports 64 single-precision operations. With a total of 64 NPUs, the chip has a total of 32 MiB of cache and a peak performance of 2 TFLOPS (single-precision).
BMDNN Chiplink
The chip incorporates Bitmain's proprietary fabric called BMDNN Chiplink technology. The fabric is a flexible, low latency link that communicates over a high-speed SerDes PHY. Two ports are available on each chip which allows multiple BM1680s to be daisy chained together to form a larger network.
In a typical configuration (i.e., a PCIe accelerator card), two BM1680s chips are wired together using chiplink. The first node in the chain is then connected to a host control (e.g., a custom ASIC unit or simply an FPGA) which provides a PCIe interface to the host processor (e.g., on a typical server a Xeon). Data from the host processor is then sent to the host controller on the accelerator unit which is then distributed across all the NPUs on all the available nodes.
Current offering by Bitmain is limited to two BM1680s chips per accelerator card, however in theory the chip can be chained to form a much larger network. The primary limitations of the network are power consumption and thermal dissipation as well as PCIe bandwidth which Bitmain requires to be x4 lanes per node (or 3.9 GB/s, 8 GT/s). For example, current offerings by Bitmain features two nodes on a PCIe Gen3 x8 card.
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
| has ecc memory support | true + |
| max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
| max memory channels | 4 + |
| supported memory type | DDR4-2666 + |