Semiconductor & Computer Engineering
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Difference between revisions of "pezy/pezy-scx/pezy-sc4"
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|first announced=2016 | |first announced=2016 | ||
|first launched=2020 | |first launched=2020 | ||
| + | |family=PEZY-SCx | ||
|frequency=1,600 MHz | |frequency=1,600 MHz | ||
|process=5 nm | |process=5 nm | ||
Revision as of 23:39, 31 October 2017
Template:mpu PEZY-SC4 (PEZY Super Computer 4) is fifth generation many-core microprocessor planned by PEZY. The SC4 incorporates 16,192 cores, twice times as many cores as its predecessor.
Planned to be fabricated on TSMC's 5 nm process, PEZY-SC5 operates at 1.6 GHz and consume around 640 W while delivering performance in the order of 210 TFLOPS (HP), 105 TFLOPS (SP), and 52.5 TFLOPS (DP).
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Memory controller
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Integrated Memory Controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Facts about "PEZY-SC4 - PEZY"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SC4 - PEZY#io + |
| has ecc memory support | true + and false + |
| max memory bandwidth | 119.2 GiB/s (122,060.8 MiB/s, 127.99 GB/s, 127,990.025 MB/s, 0.116 TiB/s, 0.128 TB/s) + and 22,886.4 GiB/s (23,435,673.6 MiB/s, 24,574.085 GB/s, 24,574,084.881 MB/s, 22.35 TiB/s, 24.574 TB/s) + |
| max memory channels | 4 + and 8 + |
| max pcie lanes | 512 + |
| supported memory type | DDR5-4000 + |