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Difference between revisions of "vti/vl86cx/vy86c061"
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'''VY86C061''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1993]]. This processor is based on the {{armh|ARM6|l=arch}} microarchitecture which was manufactured on [[VLSI Technology|VLSI]]'s [[0.8 µm process]] and operated at 20 MHz an 25 MHz.
 
'''VY86C061''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1993]]. This processor is based on the {{armh|ARM6|l=arch}} microarchitecture which was manufactured on [[VLSI Technology|VLSI]]'s [[0.8 µm process]] and operated at 20 MHz an 25 MHz.
  
This ARM6 is made pin-compatible with the original ARM2 ({{\\|VL86C010}}) and was hard wired in an ARM2 compatible mode. It's designed to serve as a drop-in upgrade for those chips.
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This ARM6 is made pin-compatible with the original ARM2 ({{\\|VL86C010}}) and was hard wired in an ARM2 compatible mode. It's designed to serve as a drop-in upgrade for those chips, therefore despite being an {{armh|ARM6|l=arch}}, it still has a {{arm|26-bit}} bus.
  
 
== Cache ==
 
== Cache ==

Revision as of 22:27, 9 September 2017

Template:mpu VY86C061 is a 32-bit ARM microprocessor designed by ARM and introduce by VTI in 1993. This processor is based on the ARM6 microarchitecture which was manufactured on VLSI's 0.8 µm process and operated at 20 MHz an 25 MHz.

This ARM6 is made pin-compatible with the original ARM2 (VL86C010) and was hard wired in an ARM2 compatible mode. It's designed to serve as a drop-in upgrade for those chips, therefore despite being an ARM6, it still has a 26-bit bus.

Cache

This processor has no integrated cache.

Datasheet