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'''Atom C3958''' is a {{arch|64}} [[hexadeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3958, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2 GHz with a [[TDP]] of 31 W. The C3958 supports up to a dual-channel of 256 GiB of DDR4-2400 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Network and Enterprise Storage SKUs]] and come with integrated {{intel|QuickAssist Technology}}.
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'''Atom C3958''' is a {{arch|64}} [[hexadeca-core]] ultra-low power [[x86]] microserver [[system on a chip]] introduced by [[Intel]] in 2017. The C3958, which is manufactured on a [[14 nm process]], is based on the {{intel|Goldmont|l=arch}} microarchitecture. This chip operates at 2 GHz with a [[TDP]] of 31 W. The C3958 supports up to 256 GiB of dual-channel DDR4-2400 [[ECC]] memory. This model is part of {{intel|Denverton|l=core}}'s [[part of::Network and Enterprise Storage SKUs]] and come with integrated {{intel|QuickAssist Technology}}.
  
 
== Cache ==
 
== Cache ==

Revision as of 01:20, 17 August 2017

Template:mpu Atom C3958 is a 64-bit hexadeca-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3958, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2 GHz with a TDP of 31 W. The C3958 supports up to 256 GiB of dual-channel DDR4-2400 ECC memory. This model is part of Denverton's Network and Enterprise Storage SKUs and come with integrated QuickAssist Technology.

Cache

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$896 KiB
917,504 B
0.875 MiB
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L1D$384 KiB
393,216 B
0.375 MiB
16x24 KiB6-way set associativewrite-back
L2$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  8x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3L-1600, DDR4-2400
Supports ECCYes
Max Mem256 GiB
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
36,618.24 MiB/s
38.397 GB/s
38,397.008 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s

Expansions

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as any combination of the following:

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 20
Configuration: x8, x4, x2
USBRevision: 3.0
Max Ports: 8
SATARevision: 3.0
Max Ports: 16
HSIOMax Lanes: 20


Features

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Facts about "Atom C3958 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Atom C3958 - Intel#pcie +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions + and Integrated QuickAssist Technology +
has integrated intel quickassist technologytrue +
has intel enhanced speedstep technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size896 KiB (917,504 B, 0.875 MiB) +
l1d$ description6-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description16-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
max hsio lanes20 +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
max sata ports16 +
max usb ports8 +
part ofNetwork and Enterprise Storage SKUs +
supported memory typeDDR3L-1600 + and DDR4-2400 +
x86/has memory protection extensionstrue +