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Difference between revisions of "renesas/r-car/e2"
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|v core=1.0 V | |v core=1.0 V | ||
|v io=3.3 V | |v io=3.3 V |
Revision as of 15:23, 22 July 2017
Template:mpu R-Car E2 is an entry-level embedded tri-core SoC designed by Renesas for the automotive industry and introduced in late 2014. The E2 incorporates two Cortex-A7 cores operating at 1 GHz along with a SH-4A core operating at 780 MHz for real-time processing. This chip includes an Imagination PowerVR SGX540 GPU operating at 260 MHz and supports up to 2 GiB of dual-channel DDR3-1333 memory.
Cache
- Main article: Cortex-A7 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
- Flash ROM and SRAM, Data bus width: 8 or 16 bits
- USB 2.0 host interface × 2 ports (wPHY)
- SD host interface × 3 ch (SDXC, UHS-I)
- Multimedia card interface × 1 ch
- I²C bus interface × 8 ch
- Serial communication interface (SCIF) × 18 ch
- Quad serial peripheral interface (QSPI) × 1 ch (for boot)
- Clock-synchronized serial interface (MSIOF) × 3 ch (SPI/IIS)
- Ethernet AVB controller (IEEE802.1BA/802.1AS/802.1Qav/IEEE1722, GMII/MII, without PHY)
- Ethernet controller (IEEE802.3u, RMII, without PHY)
Graphics
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Block Diagram
Facts about "R-Car E2 - Renesas"
has ecc memory support | false + |
integrated gpu | PowerVR SGX540 + |
integrated gpu base frequency | 260 MHz (0.26 GHz, 260,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 1 + |
l1$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l1i$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
max memory bandwidth | 9.93 GiB/s (10,168.32 MiB/s, 10.662 GB/s, 10,662.256 MB/s, 0.0097 TiB/s, 0.0107 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR3-1333 + |