Semiconductor & Computer Engineering
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Difference between revisions of "renesas/r-car/m1s"
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|first announced=February 16, 2011 | |first announced=February 16, 2011 | ||
|first launched=June, 2012 | |first launched=June, 2012 | ||
| − | |release price=$ | + | |release price=$65 |
|family=R-Car | |family=R-Car | ||
|series=1st Gen | |series=1st Gen | ||
Revision as of 12:10, 21 July 2017
Template:mpu R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
Cache
- Main article: Cortex-A9 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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- MLB (MOST150) 6-Pin I/F
- 2 x CAN 32 Message Buffers
- MMC
- 3 x SD
Graphics
- 20MPoly/s; 1000MPix/s; 3.2GFlops/s
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Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Block Diagram
Facts about "R-Car M1S - Renesas"
| has ecc memory support | false + |
| integrated gpu | PowerVR SGX540 + |
| integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
| integrated gpu designer | Imagination Technologies + |
| integrated gpu execution units | 2 + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| max memory bandwidth | 3.97 GiB/s (4,065.28 MiB/s, 4.263 GB/s, 4,262.755 MB/s, 0.00388 TiB/s, 0.00426 TB/s) + |
| max memory channels | 1 + |
| supported memory type | DDR3-1066 + and DDR2-800 + |