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Difference between revisions of "renesas/r-car/h1"
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'''R-Car H1''' is a high-end embedded [[penta-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features [[5 cores]], four {{armh|Cortex-A9|l=arch}} cores operating at 1 GHz and an additional {{renesas|SH-4A|l=arch}} core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chips incorporates [[Imagination]]'s {{imgtec|PowerVR SGX543}}-MP2 [[GPU]]. The H1 supports up to 2 GiB of DDR3-1066 memory.
 
'''R-Car H1''' is a high-end embedded [[penta-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features [[5 cores]], four {{armh|Cortex-A9|l=arch}} cores operating at 1 GHz and an additional {{renesas|SH-4A|l=arch}} core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chips incorporates [[Imagination]]'s {{imgtec|PowerVR SGX543}}-MP2 [[GPU]]. The H1 supports up to 2 GiB of DDR3-1066 memory.
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 +
== Cache ==
 +
{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l2 cache=1 MiB
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|l2 break=4x256 KiB
 +
}}
 +
 +
== Memory controller ==
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{{memory controller
 +
|type=DDR3-1066
 +
|ecc=No
 +
|max mem=2 GiB
 +
|controllers=1
 +
|channels=2
 +
|width=32 bit
 +
|max bandwidth=7.95 GiB/s
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|bandwidth schan=3.97 GiB/s
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|bandwidth dchan=7.95 GiB/s
 +
}}
 +
 +
== Expansions ==
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{{expansions
 +
| pcie revision      = 2.0
 +
| pcie lanes        = 1
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| pcie config        = 1x1
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| usb revision      = 2.0
 +
| usb ports          = 2
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| usb rate          = 480 Mbps
 +
| uart              = Yes
 +
| uart ports        = 8
 +
| sata revision      = 3.0
 +
| sata ports        = 1
 +
| i2c                = Yes
 +
| i2c ports          = 4
 +
| gp io              = Yes
 +
| jtag              = Yes
 +
}}
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* 3 x HSPI
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* MLB (MOST150) 6-Pin I/F
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* 2 x CAN 32 Message Buffers
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* MMC
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* 4 x SD
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== Graphics ==
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{{integrated graphics
 +
| gpu                = PowerVR SGX543
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| designer            = Imagination Technologies
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| execution units    = 2
 +
| max displays        = 2
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| frequency          = 250 MHz
 +
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| output crt          =
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| output sdvo        =
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| output dsi          =
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| output edp          = Yes
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| output dp          = Yes
 +
| output hdmi        = Yes
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| output vga          =
 +
| output dvi          = Yes
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| opengl es ver      = 2.0
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| opengl ver          = 2.0
 +
| opencl ver          = 1.1
 +
| directx            = 9.0 L1
 +
}}

Revision as of 21:43, 20 July 2017

Template:mpu R-Car H1 is a high-end embedded penta-core SoC for the automotive industry designed by Renesas and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features 5 cores, four Cortex-A9 cores operating at 1 GHz and an additional SH-4A core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chips incorporates Imagination's PowerVR SGX543-MP2 GPU. The H1 supports up to 2 GiB of DDR3-1066 memory.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels2
Width32 bit
Max Bandwidth7.95 GiB/s
8,140.8 MiB/s
8.536 GB/s
8,536.248 MB/s
0.00776 TiB/s
0.00854 TB/s
Bandwidth
Single 3.97 GiB/s
Double 7.95 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision2.0
Max Lanes1
Configs1x1
USB
Revision2.0
Ports2
Rate480 Mbps
UART
Ports8
SATA
Revision3.0
Ports1
I²C
Ports4
GP I/OYes
JTAGYes
  • 3 x HSPI
  • MLB (MOST150) 6-Pin I/F
  • 2 x CAN 32 Message Buffers
  • MMC
  • 4 x SD

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX543
DesignerImagination Technologies
Execution Units2Max Displays2
Frequency250 MHz
0.25 GHz
250,000 KHz
OutputDP, eDP, HDMI, DVI
Standards
OpenGL2.0
OpenCL1.1
OpenGL ES2.0
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Facts about "R-Car H1 - Renesas"
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R-Car H1 - Renesas#io +
has ecc memory supportfalse +
integrated gpuPowerVR SGX543 +
integrated gpu base frequency250 MHz (0.25 GHz, 250,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units2 +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth7.95 GiB/s (8,140.8 MiB/s, 8.536 GB/s, 8,536.248 MB/s, 0.00776 TiB/s, 0.00854 TB/s) +
max memory channels2 +
max pcie lanes1 +
supported memory typeDDR3-1066 +