Semiconductor & Computer Engineering
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Difference between revisions of "renesas/r-car/h1"
| Line 8: | Line 8: | ||
|model number=H1 | |model number=H1 | ||
|part number=R8A77790 | |part number=R8A77790 | ||
| − | |first announced=October 21, | + | |first announced=October 21, 2011 |
| − | |first launched= | + | |first launched=November, 2011 |
|family=R-Car | |family=R-Car | ||
|series=H | |series=H | ||
| Line 28: | Line 28: | ||
|package module 1={{packages/renesas/fcbga-832}} | |package module 1={{packages/renesas/fcbga-832}} | ||
}} | }} | ||
| + | '''R-Car H1''' is a high-end embedded [[penta-core]] SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features [[5 cores]], four {{armh|Cortex-A9|l=arch}} cores operating at 1 GHz and an additional {{renesas|SH-4A|l=arch}} core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chips incorporates [[Imagination]]'s {{imgtec|PowerVR SGX543}}-MP2 [[GPU]]. The H1 supports up to 2 GiB of DDR3-1066 memory. | ||
Revision as of 21:19, 20 July 2017
Template:mpu R-Car H1 is a high-end embedded penta-core SoC for the automotive industry designed by Renesas and introduced in 2011. While mass production was scheduled to begin in December 2012, it's unknown if that stage was ever actually reached. The H1 features 5 cores, four Cortex-A9 cores operating at 1 GHz and an additional SH-4A core operating at 800 MHz intended for real-time processing multimedia engine (MME). This chips incorporates Imagination's PowerVR SGX543-MP2 GPU. The H1 supports up to 2 GiB of DDR3-1066 memory.