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Difference between revisions of "ibm/microarchitectures/z900"
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|designer=IBM | |designer=IBM | ||
|manufacturer=IBM | |manufacturer=IBM | ||
+ | |introduction=October 3, 2000 | ||
+ | |phase-out=June 30, 2006 | ||
+ | |process=0.180 µm | ||
+ | |cores=12 | ||
+ | |cores 2=20 | ||
+ | |type=Scalar | ||
+ | |type 2=Pipelined | ||
+ | |oooe=No | ||
+ | |speculative=Yes | ||
+ | |renaming=No | ||
+ | |stages=7 | ||
+ | |isa=z/Architecture | ||
+ | |l1i=256 KiB | ||
+ | |l1i per=core | ||
+ | |l1d=256 KiB | ||
+ | |l1d per=core | ||
+ | |l2=8-16 MiB | ||
+ | |l2 per=cluster | ||
}} | }} | ||
'''z900''' was a [[z/Architecture]]-based microarchitecture designed by [[IBM]] and introduced in 2000 for their {{ibm|z900}} processors and 2064-series mainframes. | '''z900''' was a [[z/Architecture]]-based microarchitecture designed by [[IBM]] and introduced in 2000 for their {{ibm|z900}} processors and 2064-series mainframes. |
Revision as of 17:17, 19 July 2017
Edit Values | |
z900 µarch | |
General Info | |
Arch Type | CPU |
Designer | IBM |
Manufacturer | IBM |
Introduction | October 3, 2000 |
Phase-out | June 30, 2006 |
Process | 0.180 µm |
Core Configs | 12, 20 |
Pipeline | |
Type | Scalar, Pipelined |
OoOE | No |
Speculative | Yes |
Reg Renaming | No |
Stages | 7 |
Instructions | |
ISA | z/Architecture |
Cache | |
L1I Cache | 256 KiB/core |
L1D Cache | 256 KiB/core |
L2 Cache | 8-16 MiB/cluster |
z900 was a z/Architecture-based microarchitecture designed by IBM and introduced in 2000 for their z900 processors and 2064-series mainframes.
Facts about "z900 - Microarchitectures - IBM"
codename | z900 + |
core count | 12 + and 20 + |
designer | IBM + |
first launched | October 3, 2000 + |
full page name | ibm/microarchitectures/z900 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | IBM + |
microarchitecture type | CPU + |
name | z900 + |
phase-out | June 30, 2006 + |
pipeline stages | 7 + |
process | 180 nm (0.18 μm, 1.8e-4 mm) + |