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Difference between revisions of "intel/xeon gold/6126"
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== Frequencies ==
 
== Frequencies ==
 
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
−
{{frequency table}}
+
{{frequency table
 +
|freq_base=2,600 MHz
 +
|freq_1=3,700 MHz
 +
|freq_2=3,700 MHz
 +
|freq_3=3,500 MHz
 +
|freq_4=3,500 MHz
 +
|freq_5=3,400 MHz
 +
|freq_6=3,400 MHz
 +
|freq_7=3,400 MHz
 +
|freq_8=3,400 MHz
 +
|freq_9=3,300 MHz
 +
|freq_10=3,300 MHz
 +
|freq_11=3,300 MHz
 +
|freq_12=3,300 MHz
 +
|freq_avx2_base=2,200 MHz
 +
|freq_avx2_1=3,600 MHz
 +
|freq_avx2_2=3,600 MHz
 +
|freq_avx2_3=3,400 MHz
 +
|freq_avx2_4=3,400 MHz
 +
|freq_avx2_5=3,300 MHz
 +
|freq_avx2_6=3,300 MHz
 +
|freq_avx2_7=3,300 MHz
 +
|freq_avx2_8=3,300 MHz
 +
|freq_avx2_9=2,900 MHz
 +
|freq_avx2_10=2,900 MHz
 +
|freq_avx2_11=2,900 MHz
 +
|freq_avx2_12=2,900 MHz
 +
|freq_avx512_base=1,700 MHz
 +
|freq_avx512_1=3,500 MHz
 +
|freq_avx512_2=3,500 MHz
 +
|freq_avx512_3=3,300 MHz
 +
|freq_avx512_4=3,300 MHz
 +
|freq_avx512_5=2,600 MHz
 +
|freq_avx512_6=2,600 MHz
 +
|freq_avx512_7=2,600 MHz
 +
|freq_avx512_8=2,600 MHz
 +
|freq_avx512_9=2,300 MHz
 +
|freq_avx512_10=2,300 MHz
 +
|freq_avx512_11=2,300 MHz
 +
|freq_avx512_12=2,300 MHz
 +
}}

Revision as of 23:22, 16 July 2017

Template:mpu Xeon Gold 6126 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6126, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.6 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

The Xeon Gold 6126 features a considerably larger non-default 19.25 MiB of L3, a size that would normally be found on a 14-core part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
  14x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112
Normal2,600 MHz3,700 MHz3,700 MHz3,500 MHz3,500 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz
AVX22,200 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,300 MHz3,300 MHz3,300 MHz3,300 MHz2,900 MHz2,900 MHz2,900 MHz2,900 MHz
AVX5121,700 MHz3,500 MHz3,500 MHz3,300 MHz3,300 MHz2,600 MHz2,600 MHz2,600 MHz2,600 MHz2,300 MHz2,300 MHz2,300 MHz2,300 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6126&oldid=55031"
Facts about "Xeon Gold 6126 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6126 - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
supported memory typeDDR4-2666 +