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Difference between revisions of "intel/xeon platinum/8176f"
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'''Xeon Platinum 8176F''' is a {{arch|64}} [[28-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8176F, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 173 W and a {{intel|turbo boost}} frequency of up to 3.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
 
'''Xeon Platinum 8176F''' is a {{arch|64}} [[28-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8176F, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.1 GHz with a TDP of 173 W and a {{intel|turbo boost}} frequency of up to 3.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
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== Cache ==
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
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{{cache size
 +
|l1 cache=1.75 MiB
 +
|l1i cache=896 KiB
 +
|l1i break=28x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=896 KiB
 +
|l1d break=28x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=28 MiB
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|l2 break=28x1 MiB
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|l2 desc=16-way set associative
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|l2 policy=write-back
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|l3 cache=38.5 MiB
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|l3 break=28x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 04:16, 12 July 2017

Template:mpu Xeon Platinum 8176F is a 64-bit 28-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8176F, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 173 W and a turbo boost frequency of up to 3.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.75 MiB
1,792 KiB
1,835,008 B
L1I$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associative 
L1D$896 KiB
917,504 B
0.875 MiB
28x32 KiB8-way set associativewrite-back
L2$28 MiB
28,672 KiB
29,360,128 B
0.0273 GiB
  28x1 MiB16-way set associativewrite-back
L3$38.5 MiB
39,424 KiB
40,370,176 B
0.0376 GiB
  28x1.375 MiB11-way set associativewrite-back
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Facts about "Xeon Platinum 8176F - Intel"
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l1$ size1,792 KiB (1,835,008 B, 1.75 MiB) +
l1d$ description8-way set associative +
l1d$ size896 KiB (917,504 B, 0.875 MiB) +
l1i$ description8-way set associative +
l1i$ size896 KiB (917,504 B, 0.875 MiB) +
l2$ description16-way set associative +
l2$ size28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) +
l3$ description11-way set associative +
l3$ size38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) +