From WikiChip
Difference between revisions of "intel/xeon platinum/8153"
Line 39: | Line 39: | ||
'''Xeon Platinum 8153''' is a {{arch|64}} [[16-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8153, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | '''Xeon Platinum 8153''' is a {{arch|64}} [[16-core]] [[x86]] multi-socket highest performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8153, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. | ||
− | == | + | == Cache == |
− | {{ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
− | | | + | {{cache size |
− | | | + | |l1 cache=1 MiB |
− | + | |l1i cache=512 KiB | |
− | + | |l1i break=16x32 KiB | |
− | + | |l1i desc=8-way set associative | |
− | + | |l1d cache=512 KiB | |
− | + | |l1d break=16x32 KiB | |
− | + | |l1d desc=8-way set associative | |
− | + | |l1d policy=write-back | |
− | + | |l2 cache=16 MiB | |
− | + | |l2 break=16x1 MiB | |
− | + | |l2 desc=16-way set associative | |
− | + | |l2 policy=write-back | |
− | + | |l3 cache=22 MiB | |
− | + | |l3 break=16x1.375 MiB | |
− | + | |l3 desc=11-way set associative | |
− | + | |l3 policy=write-back | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
− | | | ||
}} | }} |
Revision as of 03:11, 12 July 2017
Template:mpu Xeon Platinum 8153 is a 64-bit 16-core x86 multi-socket highest performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 8-way multiprocessing. The Platinum 8153, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2 GHz with a TDP of 125 W and a turbo boost frequency of up to 2.8 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||||||||||||||
|
Facts about "Xeon Platinum 8153 - Intel"
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |