From WikiChip
Difference between revisions of "intel/xeon gold/6130t"
< intel‎ | xeon gold

Line 170: Line 170:
 
|amdtsme=No
 
|amdtsme=No
 
|amdsev=No
 
|amdsev=No
|rvi=No
 
|smt=No
 
|sensemi=No
 
|xfr=No
 
}}
 
{{x86 features
 
|real=Yes
 
|protected=Yes
 
|smm=Yes
 
|fpu=Yes
 
|x8616=Yes
 
|x8632=Yes
 
|x8664=Yes
 
|nx=Yes
 
|mmx=Yes
 
|emmx=Yes
 
|sse=Yes
 
|sse2=Yes
 
|sse3=Yes
 
|ssse3=Yes
 
|sse41=Yes
 
|sse42=Yes
 
|sse4a=No
 
|avx=Yes
 
|avx2=Yes
 
 
|abm=Yes
 
|tbm=No
 
|bmi1=Yes
 
|bmi2=Yes
 
|fma3=Yes
 
|fma4=No
 
|aes=Yes
 
|rdrand=Yes
 
|sha=No
 
|xop=No
 
|adx=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|tbt1=No
 
|tbt2=No
 
|tbmt3=No
 
|bpt=No
 
|eist=Yes
 
|sst=No
 
|flex=No
 
|fastmem=No
 
|isrt=No
 
|sba=No
 
|mwt=No
 
|sipp=No
 
|att=No
 
|ipt=No
 
|tsx=Yes
 
|txt=No
 
|ht=Yes
 
|vpro=Yes
 
|vtx=Yes
 
|vtd=Yes
 
|ept=Yes
 
|mpx=Yes
 
|sgx=No
 
|securekey=No
 
|osguard=Yes
 
|3dnow=No
 
|e3dnow=No
 
|smartmp=No
 
|powernow=No
 
|amdvi=No
 
|amdv=No
 
 
|rvi=No
 
|rvi=No
 
|smt=No
 
|smt=No

Revision as of 00:23, 12 July 2017

Template:mpu Xeon Gold 6130T is a 64-bit 16-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6130T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 125 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1 MiB
1,024 KiB
1,048,576 B
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back

L2$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  16x1 MiB16-way set associativewrite-back

L3$22 MiB
22,528 KiB
23,068,672 B
0.0215 GiB
  16x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Gold 6130T - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size1,024 KiB (1,048,576 B, 1 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description16-way set associative +
l2$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
l3$ description11-way set associative +
l3$ size22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
max pcie lanes48 +
supported memory typeDDR4-2666 +