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Difference between revisions of "intel/xeon gold/6148"
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{{intel title|Xeon Gold 6148}} | {{intel title|Xeon Gold 6148}} | ||
{{mpu | {{mpu | ||
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|name=Xeon Gold 6148 | |name=Xeon Gold 6148 | ||
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|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
|designer=Intel | |designer=Intel | ||
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|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|word size=64 bit | |word size=64 bit | ||
|core count=20 | |core count=20 | ||
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|max cpus=4 | |max cpus=4 | ||
|max memory=768 GiB | |max memory=768 GiB | ||
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|tdp=150 W | |tdp=150 W | ||
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|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=86 °C | |tcase max=86 °C | ||
|package module 1={{packages/intel/fclga-3647}} | |package module 1={{packages/intel/fclga-3647}} | ||
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}} | }} | ||
| − | '''Xeon Gold 6148''' is a {{arch|64}} [[ | + | '''Xeon Gold 6148''' is a {{arch|64}} [[20-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6148, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.4 GHz with a TDP of 150 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory. |
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== Cache == | == Cache == | ||
Revision as of 23:33, 11 July 2017
Template:mpu Xeon Gold 6148 is a 64-bit 20-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6148, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.4 GHz with a TDP of 150 W and a turbo boost frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 6148 - Intel"
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions + and OS Guard + |
| has intel enhanced speedstep technology | true + |
| has intel supervisor mode execution protection | true + |
| has intel vpro technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| supported memory type | DDR4-2666 + |
| x86/has memory protection extensions | true + |