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Difference between revisions of "intel/xeon bronze/3104"
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{{intel title|Xeon Bronze 3104}}
 
{{intel title|Xeon Bronze 3104}}
 
{{mpu
 
{{mpu
−
|future=Yes
 
 
|name=Xeon Bronze 3104
 
|name=Xeon Bronze 3104
−
|no image=Yes
+
|image=skylake sp (basic).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=3104
 
|model number=3104
−
|part number=CD8067303562000
+
|part number=BX806733104
 +
|part number 2=CD8067303562000
 +
|s-spec=SR3GM
 
|market=Server
 
|market=Server
 +
|market 2=Workstation
 +
|first announced=July 11, 2017
 +
|first launched=July 11, 2017
 +
|release price=$213.00
 
|family=Xeon Bronze
 
|family=Xeon Bronze
 
|series=3000
 
|series=3000
 
|locked=Yes
 
|locked=Yes
 
|frequency=1,700 MHz
 
|frequency=1,700 MHz
 +
|clock multiplier=17
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
Line 20: Line 26:
 
|core name=Skylake SP
 
|core name=Skylake SP
 
|core family=6
 
|core family=6
 +
|core stepping=U0
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 26: Line 33:
 
|thread count=12
 
|thread count=12
 
|max cpus=2
 
|max cpus=2
 +
|max memory=768 GiB
 +
|tcase min=0 °C
 +
|tcase max=79 °C
 
|package module 1={{packages/intel/fclga-3647}}
 
|package module 1={{packages/intel/fclga-3647}}
 
}}
 
}}

Revision as of 13:03, 11 July 2017

Template:mpu Xeon Bronze 3104 is a 64-bit hexa-core x86 server microprocessor set to be introduced by Intel in July 2017. This processor operates at 1.7 GHz.

DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associativewrite-back
L2$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  6x1 MiB16-way set associativewrite-back
L3$8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
  6x1.375 MiB11-way set associativewrite-back
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Facts about "Xeon Bronze 3104 - Intel"
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l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description16-way set associative +
l2$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description11-way set associative +
l3$ size8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +