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{{x86 title|AVX-512}}{{x86 isa main}}
 
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'''AVX-512''' is collective name for a number of {{arch|512}} [[SIMD]] [[x86]] [[instruction set]] extensions. The {{x86|extensions}} were formally introduced by [[Intel]] in July [[2013]] with first general-purpose microprocessors implementing the extension introduced in July [[2017]].
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'''AVX-512''' is collective name for a number of {{arch|512}} [[SIMD]] [[x86]] [[instruction set]] extensions. The {{x86|extensions}} were formally introduced by [[Intel]] in July [[2013]] with first general-purpose microprocessors implementing the extensions introduced in July [[2017]].
  
 
== Overview ==
 
== Overview ==

Revision as of 23:57, 10 July 2017

x86
Instruction Set Architecture
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AVX-512 is collective name for a number of 512-bit SIMD x86 instruction set extensions. The extensions were formally introduced by Intel in July 2013 with first general-purpose microprocessors implementing the extensions introduced in July 2017.

Overview

AVX-512 is a set of 512-bit SIMD extensions that allow programs to pack sixteen single-precision eight double-precision floating-point numbers, or eight 64-bit or sixteen 32-bit integers within 512-bit vectors. The extension provides double the computation capabilities of that of AVX/AV2.

  • AVX512F - AVX-512 Foundation is base of the 512-bit SIMD instruction extensions which is a comprehensive list of features for most HPC and enterprise applications. AVX-512 Foundation is the natural extensions to AVX/AVX2 which is extended using the EVEX prefix which builds on the existing VEX prefix. Any processor that implements any portion of the AVX-512 extensions MUST implement AVX512F.
  • AVX512PF - AVX-512 Prefetch Instructions add new prefetch instructions for gather/scatter and PREFETCHWT1 .
  • AVX512VL - AVX-512 Vector Length Instructions add vector length orthogonality, allowing most AVX-512 operations to also operate on XMM (128-bit SSE) registers and YMM (256-bit AVX) registers

Note that,

  • Formerly, the term AVX3.1 referred to F + CD + ER + PF.
  • Formerly, the term AVX3.2 referred to F + CD + BW + DQ + VL.

Detection

CPUID Instruction Set
Input Output
EAX=07H, ECX=0 EBX[bit 16] AVX512F
EBX[bit 17] AVX512DQ
EBX[bit 21] AVX512IFMA
EBX[bit 26] AVX512PF
EBX[bit 27] AVX512ER
EBX[bit 28] AVX512CD
EBX[bit 30] AVX512BW
EBX[bit 31] AVX512VL
ECX[bit 01] AVX512VBMI
ECX[bit 14] AVX512VPOPCNTDQ
EDX[bit 02] AVX5124VNNIW
EDX[bit 03] AVX5124FMAPS

Implementation

Designer Microarchitecture Support Level
F CD ER PF BW DQ VL IFMA VBMI 4FMAPS 4VNNIW VPOPCNTDQ
Intel Knights Landing ✔ ✔ ✔ ✔ ✘ ✘ ✘ ✘ ✘ ✘ ✘ ✘
Knights Milll ✔ ✔ ✔ ✔ ✘ ✘ ✘ ✘ ✘ ✔ ✔ ✔
Skylake ✔ ✔ ✘ ✘ ✔ ✔ ✔ ✘ ✘ ✘ ✘ ✘
Cannonlake ✔ ✔ ✘ ✘ ✔ ✔ ✔ ✔ ✔ ✘ ✘ ✘
Icelake ✔ ✔ ✘ ✘ ✔ ✔ ✔ ✔ ✔ ✘ ✘ ✘

Documents

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