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Difference between revisions of "vti/vl86cx/vy86c610"
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'''VY86C610''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1993]]. This processor is based on the {{armh|ARM6|l=arch}} microarchitecture ({{armh|ARM610|l=core}} core) which was manufactured on [[VLSI Technology|VLSI]]'s [[0.8 µm process]] and operated at 20 MHz.
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'''VY86C610''' is a {{arch|32}} [[ARM]] microprocessor designed by [[arm holdings|ARM]] and introduce by [[vti|VTI]] in [[1993]]. This processor is based on the {{armh|ARM6|l=arch}} microarchitecture ({{armh|ARM610|l=core}} core) which was manufactured on [[VLSI Technology|VLSI]]'s [[0.8 µm process]] and operated at 20 MHz and 25 MHz.
  
 
This processor, unlike its {{armh|ARM60|l=core}} variant which only incorporate the bare bone core, includes a cache, write buffer, and a [[memory management unit]].
 
This processor, unlike its {{armh|ARM60|l=core}} variant which only incorporate the bare bone core, includes a cache, write buffer, and a [[memory management unit]].

Revision as of 12:49, 1 July 2017

Template:mpu VY86C610 is a 32-bit ARM microprocessor designed by ARM and introduce by VTI in 1993. This processor is based on the ARM6 microarchitecture (ARM610 core) which was manufactured on VLSI's 0.8 µm process and operated at 20 MHz and 25 MHz.

This processor, unlike its ARM60 variant which only incorporate the bare bone core, includes a cache, write buffer, and a memory management unit.

Cache

Main article: ARM6 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$4 KiB
4,096 B
0.00391 MiB
  1x4 KiB64-way set associativewrite-through

Datasheet

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l1$ description64-way set associative +
l1$ size4 KiB (4,096 B, 0.00391 MiB) +