From WikiChip
Difference between revisions of "loongson/godson 2/2f"
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| model number = 2F | | model number = 2F | ||
| part number = PLA80 | | part number = PLA80 | ||
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| market = Desktop | | market = Desktop | ||
| first announced = July 31, 2007 | | first announced = July 31, 2007 |
Revision as of 18:53, 30 June 2017
Template:mpu Godson-2F (龙芯2F) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in mid-2008, the Godson-2F operates at up to 800 MHz consuming 5 W. This chip was manufactured on STMicroelectronics' 90 nm process.
The Godson-2F features a faster memory controller (supporting up to DDR2-667) and integrates some of the functionality of the southbridge including a PCI-X controller and more general-purpose I/O pins.
Cache
- Main article: GS464 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
This chip has integrated HyperTransport 1.0 operating at 400 MHz.
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Expansion Options
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Graphics
This chip had no integrated graphics processing unit.
Die Shot
- 90 nm process
- 51,000,000 transistors
- 43 mm² die size
Datasheet
References
- Hu, Wei-Wu, and Jian Wang. "Making effective decisions in computer architects’ real-world: Lessons and experiences with Godson-2 processor designs." Journal of Computer Science and Technology 23.4 (2008): 620-632.
Facts about "Godson-2F - Loongson"
has ecc memory support | true + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
max memory bandwidth | 9.934 GiB/s (10,172.416 MiB/s, 10.667 GB/s, 10,666.551 MB/s, 0.0097 TiB/s, 0.0107 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-667 + |