Difference between revisions of "intel/atom/z520"

Revision as of 21:12, 23 June 2017

Template:mpu Z520 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

This processor has a TDP of 2 W when Hyper-Threading is disabled and 2.2 W when enabled. Model price includes the chipset.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

56 KiB

57,344 B
0.0547 MiB

L1I$	32 KiB 32,768 B 0.0313 MiB	1x32 KiB	8-way set associative
L1D$	24 KiB 24,576 B 0.0234 MiB	1x24 KiB	6-way set associative	write-back

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		1x512 KiB	8-way set associative

Memory controller

This processor has no integrated memory controller.

Graphics

This processor has no integrated graphics.

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3

x86-16	16-bit x86
x86-32	32-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
EIST	Enhanced SpeedStep Technology
VT-x	VT-x (Virtualization)

Die Shot

See also: Bonnell § Silverthorne Die

45 nm process
9 metal layers
47,212,207 transistors
3.1 mm x 7.8 mm
24.18 mm² die size

@@ Line 51: / Line 51: @@
 | max cpus            = 1
-| electrical          = Yes
 | power               =
 | average power       = 220 mW

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Atom Z520 - Intel#package +
base frequency	1,333.33 MHz (1.333 GHz, 1,333,330 kHz) +
bus rate	533.33 MT/s (0.533 GT/s, 533,330 kT/s) +
bus speed	133.33 MHz (0.133 GHz, 133,330 kHz) +
bus type	FSB +
chipset	Poulsbo +
clock multiplier	10 +
core count	1 +
core family	6 +
core model	28 +
core name	Silverthorne +
core stepping	C0 +
core voltage (max)	1.1 V (11 dV, 110 cV, 1,100 mV) +
core voltage (min)	0.75 V (7.5 dV, 75 cV, 750 mV) +
cpuid	106C2 +
designer	Intel +
die area	24.18 mm² (0.0375 in², 0.242 cm², 24,180,000 µm²) +
die length	7.8 mm (0.78 cm, 0.307 in, 7,800 µm) +
die width	3.1 mm (0.31 cm, 0.122 in, 3,100 µm) +
family	Atom +
first announced	April 2, 2008 +
first launched	April 2, 2008 +
full page name	intel/atom/z520 +
has feature	Hyper-Threading Technology +, Enhanced SpeedStep Technology + and Intel VT-x +
has intel enhanced speedstep technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has simultaneous multithreading	true +
instance of	microprocessor +
isa	x86-32 +
isa family	x86 +
l1$ size	56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description	6-way set associative +
l1d$ size	24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description	8-way set associative +
l1i$ size	32 KiB (32,768 B, 0.0313 MiB) +
l2$ description	8-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldate	April 2, 2008 +
main image	+
main image caption	Silverthorne chip +
manufacturer	Intel +
market segment	Mobile +
max case temperature	343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count	1 +
max junction temperature	363.15 K (90 °C, 194 °F, 653.67 °R) +
max storage temperature	358.15 K (85 °C, 185 °F, 644.67 °R) +
microarchitecture	Bonnell +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	233.15 K (-40 °C, -40 °F, 419.67 °R) +
model number	Z520 +
name	Atom Z520 +
package	FCBGA-441 +
part number	AC80566UE014DW +
platform	Menlow +
power dissipation (average)	0.22 W (220 mW, 2.9502e-4 hp, 2.2e-4 kW) +
power dissipation (idle)	0.1 W (100 mW, 1.341e-4 hp, 1.0e-4 kW) +
process	45 nm (0.045 μm, 4.5e-5 mm) +
release price	$ 65.00 (€ 58.50, £ 52.65, ¥ 6,716.45) +
s-spec	SLB2H +
s-spec (qs)	QEQS +
sdp	0.96 W (960 mW, 0.00129 hp, 9.6e-4 kW) +
series	Z500 +
smp max ways	1 +
socket	BGA-441 +
tdp	2 W (2,000 mW, 0.00268 hp, 0.002 kW) +
technology	CMOS +
thread count	2 +
transistor count	47,212,207 +
word size	32 bit (4 octets, 8 nibbles) +

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Revision as of 21:12, 23 June 2017

Contents

Cache

Memory controller

Graphics

Features

Die Shot

Documents

Datasheet

Other