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Difference between revisions of "64-bit architecture"
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== 64-bit microprocessors == | == 64-bit microprocessors == | ||
+ | === [[Alpha]] === | ||
+ | <div style="margin: 30px;"> | ||
+ | '''DEC''' | ||
+ | * {{decc|Alpha}} | ||
+ | </div> | ||
+ | |||
+ | |||
+ | === [[ARM]] === | ||
+ | <div style="margin: 30px;"> | ||
+ | '''MediaTek''' | ||
+ | * {{mediatek|Helio}} | ||
+ | '''Phytium''' | ||
+ | * {{phytium|FT-1500A}} | ||
+ | </div> | ||
+ | |||
+ | === [[MIPS]] === | ||
+ | <div style="margin: 30px;"> | ||
+ | '''Cavium''' | ||
+ | {{collist | ||
+ | | count = 1 | ||
+ | | width = 750px | ||
+ | | | ||
+ | * {{cavium|OCTEON}} | ||
+ | * {{cavium|OCTEON Plus}} | ||
+ | }} | ||
+ | </div> | ||
=== [[x86]] === | === [[x86]] === | ||
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* {{intel|Xeon E5}} | * {{intel|Xeon E5}} | ||
* {{intel|Xeon E7}} | * {{intel|Xeon E7}} | ||
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</div> | </div> |
Revision as of 16:42, 23 June 2017
The 64-bit architecture is a microprocessor or computer architecture that has a datapath width or a highest operand width of 64 bits or 8 octets. These architectures typically have a matching register file with registers width of 64 bits.
Contents
64-bit microprocessors
Alpha
DEC
ARM
MIPS
Cavium
x86
AMD
- A10
- A8
- Athlon 64
- Athlon 64 X2
- Athlon II X2
- Athlon II X3
- Athlon II X4
- Athlon MP
- Athlon X2
- Athlon X4
- Athlon XP
- Athlon XP-M
- EPYC
- Geode NX
- Mobile Athlon 64
- Opteron
- Phenom II X2
- Phenom II X3
- Phenom II X4
- Phenom X3
- Phenom X4
- Ryzen 3
- Ryzen 5
- Ryzen 7
- Sempron
- Turion 64
- Turion 64 X2
- Turion II
- Turion II Ultra
- Turion X2 Ultra
Intel
Other
This list is incomplete; you can help by expanding it.
Research/University
- Princeton
This list is incomplete; you can help by expanding it.
64-bit microcontrollers
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