Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "pezy/pezy-scx/pezy-sc4"
| Line 42: | Line 42: | ||
|channels=8 | |channels=8 | ||
|max bandwidth=22.35 TiB/s | |max bandwidth=22.35 TiB/s | ||
| + | }} | ||
| + | |||
| + | == Expansions == | ||
| + | {{expansions | ||
| + | | pcie revision = 3.0 | ||
| + | | pcie lanes = 512 | ||
| + | | pcie config = x16 | ||
| + | | pcie config 2 = x8 | ||
| + | | pcie config 3 = x4 | ||
| + | | uart = Yes | ||
| + | | gp io = Yes | ||
}} | }} | ||
Revision as of 05:30, 23 June 2017
Template:mpu PEZY-SC4 (PEZY Super Computer 4) is fifth generation many-core microprocessor planned by PEZY. The SC4 incorporates 16,192 cores, twice times as many cores as its predecessor.
Planned to be fabricated on TSMC's 5 nm process, PEZY-SC5 operates at 1.6 GHz and consume around 640 W while delivering performance in the order of 210 TFLOPS (HP), 105 TFLOPS (SP), and 52.5 TFLOPS (DP).
 |
Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Memory controller
 |
Integrated Memory Controller
|
|||||||||||
|
||||||||||||
|
Integrated Memory Controller
|
|||||||||
|
||||||||||
Expansions
 |
Expansion Options
|
|||||||||||
|
||||||||||||
Facts about "PEZY-SC4 - PEZY"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SC4 - PEZY#io + |
| has ecc memory support | true + and false + |
| max memory bandwidth | 119.2 GiB/s (122,060.8 MiB/s, 127.99 GB/s, 127,990.025 MB/s, 0.116 TiB/s, 0.128 TB/s) + and 22,886.4 GiB/s (23,435,673.6 MiB/s, 24,574.085 GB/s, 24,574,084.881 MB/s, 22.35 TiB/s, 24.574 TB/s) + |
| max memory channels | 4 + and 8 + |
| max pcie lanes | 512 + |
| supported memory type | DDR5-4000 + |