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Difference between revisions of "amd/athlon mp/amsn2400dut3c"
< amd‎ | athlon mp

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| tstorage max        = 100 °C
 
| tstorage max        = 100 °C
  
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|package module 1={{packages/amd/pga-453}}
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| package 0          = OPGA-453
 
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| package 0 type      = OPGA
 
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| package 0 pins      = 453
 
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| package 0 pitch    = 1.27 mm
 
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| package 0 width    = 49.53 mm
 
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| package 0 length    = 49.53 mm
 
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| package 0 height    = 1.942
 
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| socket 0            = Socket A
 
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| socket 0 type      = PGA-462
 
 
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The '''Athlon MP 2400+''' (OPN ''AMSN2400DUT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 2 GHz with a FSB transfer rate of 266 MT/s (x15 multiplier), was manufactured on a newer [[130 nm]] copper processor technology in Fab 30 in Dresden, Germany.
 
The '''Athlon MP 2400+''' (OPN ''AMSN2400DUT3C'') based on the {{amd|Thoroughbred|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2002]] for the server and workstation market. This MPU operated at 2 GHz with a FSB transfer rate of 266 MT/s (x15 multiplier), was manufactured on a newer [[130 nm]] copper processor technology in Fab 30 in Dresden, Germany.

Revision as of 00:21, 23 June 2017

Template:mpu The Athlon MP 2400+ (OPN AMSN2400DUT3C) based on the Thoroughbred core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2002 for the server and workstation market. This MPU operated at 2 GHz with a FSB transfer rate of 266 MT/s (x15 multiplier), was manufactured on a newer 130 nm copper processor technology in Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Graphics

This MPU has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
SSEStreaming SIMD Extensions
x86-1616-bit x86
x86-3232-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
SmartMPSmartMP Technology
  • Advanced Configuration and Power Interface
    • Halt State
    • Stop Grant State

Documents

Datasheets

Others

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/athlon_mp/amsn2400dut3c&oldid=46384"
Facts about "Athlon MP 2400+ - AMD"
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has amd smartmp technologytrue +
has featureSmartMP Technology +, ACPI +, Halt State + and Stop Grant State +
has multiprocessing supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +