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Difference between revisions of "intel/xeon platinum/8164"
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| die length = | | die length = | ||
| word size = 64 bit | | word size = 64 bit | ||
| − | | core count = | + | | core count = 26 |
| − | | thread count = | + | | thread count = 52 |
| − | | max cpus = | + | | max cpus = 2 |
| max memory = | | max memory = | ||
| Line 108: | Line 108: | ||
| socket 0 type = LGA | | socket 0 type = LGA | ||
}} | }} | ||
| − | '''Xeon Platinum 8164''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 8164 operates at 2.0 GHz. | + | '''Xeon Platinum 8164''' is a {{arch|64}} [[x86]] high-performance server [[hexacosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 8164 operates at 2.0 GHz. |
{{unknown features}} | {{unknown features}} | ||
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
| + | {{cache size | ||
| + | |l1 cache=1.625 MiB | ||
| + | |l1i cache=832 KiB | ||
| + | |l1i break=26x32 KiB | ||
| + | |l1i desc=8-way set associative | ||
| + | |l1d cache=832 KiB | ||
| + | |l1d break=26x32 KiB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d policy=write-back | ||
| + | |l2 cache=26 MiB | ||
| + | |l2 break=26x1 MiB | ||
| + | |l2 desc=16-way set associative | ||
| + | |l2 policy=write-back | ||
| + | |l3 cache=35.75 MiB | ||
| + | |l3 break=26x1.375 MiB | ||
| + | |l3 desc=16-way set associative | ||
| + | |l3 policy=write-back | ||
| + | }} | ||
Revision as of 13:27, 26 May 2017
Template:mpu Xeon Platinum 8164 is a 64-bit x86 high-performance server hexacosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 8164 operates at 2.0 GHz.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Xeon Platinum 8164 - Intel"
| l1$ size | 1,664 KiB (1,703,936 B, 1.625 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 832 KiB (851,968 B, 0.813 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 832 KiB (851,968 B, 0.813 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 26 MiB (26,624 KiB, 27,262,976 B, 0.0254 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) + |