From WikiChip
Difference between revisions of "intel/xeon gold/6126"
< intel‎ | xeon gold

(more info from engineering samples)
Line 59: Line 59:
 
| die length          =  
 
| die length          =  
 
| word size          = 64 bit
 
| word size          = 64 bit
−
| core count          =  
+
| core count          = 12
−
| thread count        =  
+
| thread count        = 24
−
| max cpus            = 4
+
| max cpus            = 2
 
| max memory          =  
 
| max memory          =  
  
Line 108: Line 108:
 
| socket 0 type      = LGA
 
| socket 0 type      = LGA
 
}}
 
}}
−
'''Xeon Gold 6126''' is a {{arch|64}} [[x86]] high-performance server [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6126 operates at 2.6 GHz
+
'''Xeon Gold 6126''' is a {{arch|64}} [[x86]] high-performance server [[dodeca-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6126 operates at 2.6 GHz.
  
  
 
{{unknown features}}
 
{{unknown features}}
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
 +
{{cache size
 +
|l1 cache=768 KiB
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=384 KiB
 +
|l1d break=12x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=12 MiB
 +
|l2 break=12x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=16.5 MiB
 +
|l3 break=12x1.375 MiB
 +
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=
 +
|controllers=1
 +
|channels=6
 +
|max bandwidth=119.21 GiB/s
 +
|bandwidth schan=19.89 GiB/s
 +
|bandwidth dchan=39.72 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}

Revision as of 13:25, 26 May 2017

Template:mpu Xeon Gold 6126 is a 64-bit x86 high-performance server dodeca-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 6126 operates at 2.6 GHz.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Controllers1
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.89 GiB/s
Double 39.72 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/6126&oldid=43208"
Facts about "Xeon Gold 6126 - Intel"
RDF feed
has ecc memory supporttrue +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description16-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
supported memory typeDDR4-2666 +