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Difference between revisions of "intel/atom/z610"
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'''Atom Z610''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z610, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 800 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.2 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z610 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz.
 
'''Atom Z610''' is an ultra-low power {{arch|32}} [[x86]] system on a chip designed by [[Intel]] and introduced in early [[2010]]. The Z610, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Lincroft|l=core}} core), is fabricated on a [[45 nm process]]. This SoC incorporates a single core operating at 800 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.2 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z610 incorporates a {{imgtec|PowerVR SGX 535|GMA 600}} [[IGP]] operating at 400 MHz.
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 +
{{cache size
 +
|l1 cache=56 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=24 KiB
 +
|l1d break=1x24 KiB
 +
|l1d desc=6-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR-400
 +
|type 2=DDR2-800
 +
|ecc=No
 +
|max mem=2 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=32 bit
 +
|max bandwidth=2.98 GiB/s
 +
|bandwidth schan=2.98 GiB/s
 +
|pae=32 bit
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| usb revision      = 2.0
 +
| usb ports          = 4
 +
| uart              = Yes
 +
| gp io              = Yes
 +
}}
 +
 +
== Graphics ==
 +
This chip incroporates the "GMA 600" integrated graphics which is actually a re-branded licensed [[Imagination Technologies|Imagination]] {{imgtec|PowerVR SGX 535}} [[IGP]].
 +
{{integrated graphics
 +
| gpu                = PowerVR SGX535
 +
| device id          =
 +
| designer            = Imagination Technologies
 +
| execution units    =
 +
| max displays        = 1
 +
| max memory          = 256 MiB
 +
| frequency          = 200 MHz
 +
 +
| output dsi          = Yes
 +
| output lvds        = Yes
 +
 +
| max res dsi        = 1024x600
 +
| max res lvds        = 1366x768
 +
 +
| direct3d ver        = 9.0c
 +
| opengl ver          = 2.1
 +
| openvg ver          = 1.1
 +
| opengl es ver      = 1.1
 +
| opengl es ver 2    = 2.0
 +
 +
| features            = Yes
 +
| intel clear video  = Yes
 +
}}
 +
 +
* Supports hardware-accelerated HD video decode (MPEG4 part 2, H.264, WMV, and VC1)
 +
* Supports hardware-accelerated HD video encode (MPEG4 part 2 and H.264)
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=No
 +
|sse42=No
 +
|sse4a=No
 +
|avx=No
 +
|avx2=No
 +
|avx512=No
 +
|abm=No
 +
|tbm=No
 +
|bmi1=No
 +
|bmi2=No
 +
|fma3=No
 +
|fma4=No
 +
|aes=No
 +
|rdrand=No
 +
|sha=No
 +
|xop=No
 +
|adx=No
 +
|clmul=No
 +
|f16c=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=Yes
 +
|eist=Yes
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}

Revision as of 22:35, 22 April 2017

Template:mpu Atom Z610 is an ultra-low power 32-bit x86 system on a chip designed by Intel and introduced in early 2010. The Z610, which is based on the Bonnell microarchitecture (Lincroft core), is fabricated on a 45 nm process. This SoC incorporates a single core operating at 800 MHz with a low frequency mode of 600 MHz and a burst frequency of 1.2 GHz. The chip has a TDP of 1.3 W and supporting up to a 2 GiB of single-channel DDR2-800 memory. Additionally, the Z610 incorporates a GMA 600 IGP operating at 400 MHz.

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR-400, DDR2-800
Supports ECCNo
Max Mem2 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth2.98 GiB/s
3,051.52 MiB/s
3.2 GB/s
3,199.751 MB/s
0.00291 TiB/s
0.0032 TB/s
Bandwidth
Single 2.98 GiB/s
Physical Address (PAE)32 bit

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USB
Revision2.0
Ports4
UART
GP I/OYes


Graphics

This chip incroporates the "GMA 600" integrated graphics which is actually a re-branded licensed Imagination PowerVR SGX 535 IGP.

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX535
DesignerImagination Technologies
Max Displays1
Max Memory256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
Frequency200 MHz
0.2 GHz
200,000 KHz
OutputDSI, LVDS
Max Resolution
DSI1024x600
LVDS1366x768
Standards
Direct3D9.0c
OpenGL2.1
OpenGL ES1.1, 2.0
OpenVG1.1
Additional Features
Intel Clear Video
  • Supports hardware-accelerated HD video decode (MPEG4 part 2, H.264, WMV, and VC1)
  • Supports hardware-accelerated HD video encode (MPEG4 part 2 and H.264)

Features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/z610&oldid=41793"
Facts about "Atom Z610 - Intel"
RDF feed
has ecc memory supportfalse +
has featureHyper-Threading Technology +, Burst Performance Technology + and Enhanced SpeedStep Technology +
has intel burst performance technologytrue +
has intel enhanced speedstep technologytrue +
has simultaneous multithreadingtrue +
integrated gpuPowerVR SGX535 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu max memory256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
max memory bandwidth2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) +
max memory channels1 +
supported memory typeDDR-400 + and DDR2-800 +