From WikiChip
Difference between revisions of "intel/atom/z500"
< intel‎ | atom

Line 69: Line 69:
 
}}
 
}}
 
'''Z500''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z500, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 800 MHz with a TDP of just 650 mW and an average power of 160 mW. The MPU features a legacy 400 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets).
 
'''Z500''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z500, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 800 MHz with a TDP of just 650 mW and an average power of 160 mW. The MPU features a legacy 400 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/bonnell#Memory_Hierarchy|l1=Bonnell § Cache}}
 +
{{cache size
 +
|l1 cache=56 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=24 KiB
 +
|l1d break=1x24 KiB
 +
|l1d desc=6-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
This processor has no integrated memory controller.
 +
 +
== Graphics ==
 +
This processor has no integrated graphics.
 +
 +
== Features ==
 +
{{x86 features}}
 +
 +
== Die Shot ==
 +
{{see also|intel/microarchitectures/bonnell#Silverthorne|l1=Bonnell § Silverthorne Die}}
 +
* [[45 nm process]]
 +
* 9 metal layers
 +
* 47,212,207 transistors
 +
* 3.1 mm x 7.8 mm
 +
* 24.18 mm² die size
 +
 +
[[File:Silverthorne die shot.jpg|650px]]
 +
 +
 +
[[File:Silverthorne die shot (marked).png|650px]]

Revision as of 19:18, 1 April 2017

Template:mpu Z500 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z500, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 800 MHz with a TDP of just 650 mW and an average power of 160 mW. The MPU features a legacy 400 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).

Cache

Main article: Bonnell § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$56 KiB
57,344 B
0.0547 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$24 KiB
24,576 B
0.0234 MiB
1x24 KiB6-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

Memory controller

This processor has no integrated memory controller.

Graphics

This processor has no integrated graphics.

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features

Die Shot

See also: Bonnell § Silverthorne Die
  • 45 nm process
  • 9 metal layers
  • 47,212,207 transistors
  • 3.1 mm x 7.8 mm
  • 24.18 mm² die size

Silverthorne die shot.jpg


Silverthorne die shot (marked).png

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/atom/z500&oldid=40523"
Facts about "Atom Z500 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Atom Z500 - Intel#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +
bus rate400 MT/s (0.4 GT/s, 400,000 kT/s) +
bus speed100 MHz (0.1 GHz, 100,000 kHz) +
bus typeFSB +
chipsetPoulsbo +
clock multiplier8 +
core count1 +
core family6 +
core model28 +
core nameSilverthorne +
core steppingC0 +
core voltage (max)1.1 V (11 dV, 110 cV, 1,100 mV) +
core voltage (min)0.8 V (8 dV, 80 cV, 800 mV) +
cpuid106C2 +
designerIntel +
die area24.18 mm² (0.0375 in², 0.242 cm², 24,180,000 µm²) +
die length7.8 mm (0.78 cm, 0.307 in, 7,800 µm) +
die width3.1 mm (0.31 cm, 0.122 in, 3,100 µm) +
familyAtom +
first announcedApril 2, 2008 +
first launchedApril 2, 2008 +
full page nameintel/atom/z500 +
has featureHyper-Threading Technology + and Enhanced SpeedStep Technology +
has intel enhanced speedstep technologytrue +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
instance ofmicroprocessor +
isax86-32 +
isa familyx86 +
l1$ size56 KiB (57,344 B, 0.0547 MiB) +
l1d$ description6-way set associative +
l1d$ size24 KiB (24,576 B, 0.0234 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateApril 2, 2008 +
main imageFile:silverthorne.png +
main image captionSilverthorne chip +
manufacturerIntel +
market segmentMobile +
max case temperature343.15 K (70 °C, 158 °F, 617.67 °R) +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max storage temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
microarchitectureBonnell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature233.15 K (-40 °C, -40 °F, 419.67 °R) +
model numberZ500 +
nameAtom Z500 +
packageFCBGA-441 +
part numberAC80586UC800DE + and AC80566UC800DE +
platformMenlow +
power dissipation (average)0.16 W (160 mW, 2.1456e-4 hp, 1.6e-4 kW) +
power dissipation (idle)0.08 W (80 mW, 1.0728e-4 hp, 8.0e-5 kW) +
process45 nm (0.045 μm, 4.5e-5 mm) +
release price$ 45.00 (€ 40.50, £ 36.45, ¥ 4,649.85) +
s-specSLB6Q +
s-spec (qs)QGZU + and QGXC +
sdp0.96 W (960 mW, 0.00129 hp, 9.6e-4 kW) +
seriesZ500 +
smp max ways1 +
socketBGA-441 +
tdp0.65 W (650 mW, 8.7165e-4 hp, 6.5e-4 kW) +
technologyCMOS +
thread count2 +
transistor count47,212,207 +
word size32 bit (4 octets, 8 nibbles) +