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Difference between revisions of "intel/atom/z520"
(Created page with "{{intel title|Atom Z520}} {{mpu | name = Atom Z520 | no image = | image = silverthorne.png | image size = | caption...") |
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| frequency = 1,333.33 MHz | | frequency = 1,333.33 MHz | ||
| bus type = FSB | | bus type = FSB | ||
− | | bus speed = 533 | + | | bus speed = 133.33 MHz |
+ | | bus rate = 533.33 MT/s | ||
| clock multiplier = 10 | | clock multiplier = 10 | ||
| cpuid = 106C2 | | cpuid = 106C2 | ||
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| package module 1 = {{packages/intel/pbga-441}} | | package module 1 = {{packages/intel/pbga-441}} | ||
}} | }} | ||
− | '''Z520''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 | + | '''Z520''' is an ultra-low power {{arch|32}} [[x86]] microprocessor introduced by [[Intel]] in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the {{intel|Bonnell|l=arch}} microarchitecture ({{intel|Silverthorne|l=core}} core), is manufactured on a [[45 nm process]]. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s [[front-side bus]] capable of communicating with the {{intel|Poulsbo|l=chipset}} chipset in both low-power [[CMOS]] mode as well as normal [[GTL]] mode (which also works with other chipsets). |
Revision as of 14:39, 1 April 2017
Template:mpu Z520 is an ultra-low power 32-bit x86 microprocessor introduced by Intel in early 2008 specifically for Mobile Internet Devices (MID). The Z520, which is based on the Bonnell microarchitecture (Silverthorne core), is manufactured on a 45 nm process. This processor operates at 1.33 Ghz with a TDP of just 2 W and an average power of 220 mW. The MPU features a legacy 533 MT/s front-side bus capable of communicating with the Poulsbo chipset in both low-power CMOS mode as well as normal GTL mode (which also works with other chipsets).