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Difference between revisions of "intel/microarchitectures/gen9.5"
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| − | ! colspan="5" | Gen9 LP [[IGP]] Models !! colspan="9" | Standards | + | ! colspan="5" | Gen9.5 LP [[IGP]] Models !! colspan="9" | Standards |
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! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !! rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]] | ! rowspan="2" | Name !! rowspan="2" | Execution Units !! rowspan="2" | Tier !! rowspan="2" | Series !! rowspan="2" | eDRAM !! colspan="2" | [[Vulkan]] !! colspan="3" | [[Direct3D]] !! colspan="2" | [[OpenGL]] !! colspan="2" | [[OpenCL]] | ||
Revision as of 20:58, 26 January 2017
| Edit Values | |
| Gen9.5 LP µarch | |
| General Info | |
| Arch Type | GPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | August 30, 2016 |
| Process | 14 nm |
| Succession | |
Gen9.5 LP (Generation 9.5 Low Power) is the microarchitecture for Intel's graphics processing unit utilized by Kaby Lake-based microprocessors. Gen9.5 LP is the successor to Gen9 LP used by Skylake and introduces a number of light enhancements.
Codenames
Various models support different Graphics Tiers (GT) which provides different levels of performance. Some models also support an additional eDRAM side cache.
| Code Name | Description |
|---|---|
| GT1 | Contains 1 slice with 12 execution units. |
| GT2 | Contains 1 slice with 24 execution units. |
| GT3 | Contains 2 slices with 48 execution units. |
| GT3e | Contains 2 slices with 48 execution units. Has an additional eDRAM side cache. |
| Halo (GT4e) | Contains 3 slices with 72 execution units. Has an additional eDRAM side cache. |
Models
| Gen9.5 LP IGP Models | Standards | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Name | Execution Units | Tier | Series | eDRAM | Vulkan | Direct3D | OpenGL | OpenCL | |||||
| Windows | Linux | Windows | Linux | HLSL | Windows | Linux | Windows | Linux | |||||
| HD Graphics 610 | 12 | GT1 | S, U | - | 1.0 | 12 | N/A | 5.1 | 4.4 | 4.5 | 2.0 | ||
| HD Graphics 615 | 24 | GT2 | Y | - | |||||||||
| HD Graphics 620 | 24 | GT2 | U | - | |||||||||
| HD Graphics 630 | 24 | GT2 | S, H | - | |||||||||
| HD Graphics P630 | 24 | GT2 | H | - | |||||||||
| Iris Plus Graphics 640 | 48 | GT3e | U | 64 MiB | |||||||||
| Iris Plus Graphics 650 | 48 | GT3e | U | 64 MiB | |||||||||
Facts about "Gen9.5 - Microarchitectures - Intel"
| codename | Gen9.5 LP + |
| designer | Intel + |
| first launched | August 30, 2016 + |
| full page name | intel/microarchitectures/gen9.5 + |
| instance of | microarchitecture + |
| manufacturer | Intel + |
| microarchitecture type | GPU + |
| name | Gen9.5 LP + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |