Difference between revisions of "intel/xeon e3/e3-1275 v6"

Revision as of 02:44, 18 January 2017

Template:mpu Xeon E3-1275 v6 is a 64-bit quad-core x86 workstation/entry server microprocessor set to be introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The E3-1245 v6 operates at 3.8 GHz with a TDP of 78 W supporting a Turbo Boost frequency of ? GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory and incorporates Intel's HD Graphics P630 IGP operating at 400 MHz with a burst frequency of ? GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	4-way set associative	write-back

L3$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		4x2 MiB	16-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR3L-1600, LPDDR3-2133, DDR4-2400
Supports ECC	Yes
Max Mem	64 GiB
Controllers	1
Channels	2
Max Bandwidth	35.76 GiB/s 36,618.24 MiB/s 38.397 GB/s 38,397.008 MB/s 0.0349 TiB/s 0.0384 TB/s
Bandwidth	Single 17.88 GiB/s Double 35.76 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	16
Configs	1x16, 2x8, 1x8+2x4

Graphics

[Edit/Modify IGP Info]

Integrated Graphics Information

GPU

HD Graphics P630

Designer

Intel

Device ID

0x591D

Execution Units

24

Max Displays

3

Max Memory

64 GiB

65,536 MiB
67,108,864 KiB
68,719,476,736 B

Frequency

400 MHz

0.4 GHz
400,000 KHz

Burst Frequency

? MHz

"? MHz" is not a number.

Output

DP, eDP, HDMI, DVI

Max Resolution

HDMI	4096x2304 @30 Hz
DP	4096x2304 @60 Hz
eDP	4096x2304 @60 Hz

Standards

DirectX	12
OpenGL	4.4
OpenCL	2.0
DP	1.2
eDP	1.4
HDMI	1.4a

Additional Features

Intel Quick Sync Video

Intel InTru 3D

Intel Clear Video

Intel Clear Video HD

[Edit] Kaby Lake (Gen9.5) Hardware Accelerated Video Capabilities
Codec	Encode			Decode
Codec	Profiles	Levels	Max Resolution	Profiles	Levels	Max Resolution
MPEG-2 (H.262)	Main	High	1080p (FHD)	Main	Main, High	1080p (FHD)
MPEG-4 AVC (H.264)	High, Main	5.1	2160p (4K)	Main, High, MVC, Stereo	5.1	2160p (4K)
JPEG/MJPEG	Baseline	-	16k x 16k	Baseline	Unified	16k x 16k
HEVC (H.265)	Main, Main 10	5.1	2160p (4K)	Main, Main 10	5.1	2160p (4K)
VC-1	✘			Advanced, Main, Simple	3, High, Simple	3840x3840
VP8	Unified	Unified	N/A	0	Unified	1080p
VP9	0		2160p (4K)	0, 2	Unified	2160p (4K)

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
SGX	Software Guard Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology
Flex Memory	Flex Memory Access
ISRT	Smart Response Technology
MWT	My WiFi Technology
SIPP	Stable Image Platform Program

@@ Line 10: / Line 10: @@
 | manufacturer        = Intel
 | model number        = E3-1275 v6
-| part number         =
+| part number         = BX80677E31275V6
 | part number 2       =
+| s-spec              =
 | market              = Workstation
 | first announced     =
@@ Line 30: / Line 31: @@
 | bus speed           =
 | bus rate            = 8 GT/s
-| clock multiplier    =
+| bus links           =
-| s-spec              =
+| clock multiplier    = 38
-| s-spec es           =
-| s-spec qs           =
 | cpuid               =
+| isa family          = x86
+| isa                 = x86-64
 | microarch           = Kaby Lake
-| platform            =
+| platform            = Greenlow
-| chipset             =
+| chipset             = Sunrise Point
-| core name           =
+| chipset 2           = Union Point
+| core name           = Kaby Lake DT
 | core family         =
 | core model          =
 | core stepping       =
+| core stepping 2     =
 | process             = 14 nm
 | transistors         =
 | technology          = CMOS
-| die size            =
+| die area            =
+| die width           =
+| die length          =
 | word size           = 64 bit
 | core count          = 4
@@ Line 54: / Line 59: @@
 | electrical          = Yes
-| v core              =
+| v core min          =
-| v core tolerance    =
+| v core max          =
 | sdp                 =
 | tdp                 = 78 W
+| tdp typical         =
 | ctdp down           =
 | ctdp down frequency =
 | ctdp up             =
 | ctdp up frequency   =
-| temp max            =
+| tjunc min           =
-| temp min            =
+| tjunc max           =
+| tcase min           =
+| tcase max           =
+| tstorage min        = -25 °C
+| tstorage max        = 125 °C
+| tambient min        =
+| tambient max        =
-| packaging           =
+| package module 1    = {{packages/intel/lga-1151}}
-| package             =
-| package type        =
-| package size        =
-| socket              =
-| socket type         =
 }}
-The '''Xeon E3-1275 v6''' is a {{arch|64}} [[quad-core]] [[x86]] microprocessor set to be introduced by [[Intel]] in late 2016 or early 2017. Operating at 3.8 GHz, this MPU has a TDP of 78 W. This processor is a {{intel|Kaby Lake}}-based chip and is manufactured on a Intel's [[14 nm process]].
+'''Xeon E3-1275 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor set to be introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1245 v6 operates at 3.8 GHz with a TDP of 78 W supporting a {{intel|Turbo Boost}} frequency of ? GHz. The processor supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 400 MHz with a burst frequency of ? GHz.
@@ Line 130: / Line 137: @@
 | max memory          = 64 GiB
 | frequency           = 400 MHz
-| max frequency       = 1,150 MHz
+| max frequency       = ? MHz
 | output crt          =

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon E3-1275 v6 - Intel#package + and Xeon E3-1275 v6 - Intel#io +
base frequency	3,800 MHz (3.8 GHz, 3,800,000 kHz) +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Sunrise Point + and Union Point +
clock multiplier	38 +
core count	4 +
core family	6 +
core model	158 +
core name	Kaby Lake DT +
core stepping	B0 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.55 V (5.5 dV, 55 cV, 550 mV) +
designer	Intel +
device id	0x591D +
family	Xeon E3 +
first announced	March 28, 2017 +
first launched	March 28, 2017 +
full page name	intel/xeon e3/e3-1275 v6 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology + and OS Guard +
has intel enhanced speedstep technology	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics P630 +
integrated gpu base frequency	350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	24 +
integrated gpu max frequency	1,150 MHz (1.15 GHz, 1,150,000 KHz) +
integrated gpu max memory	1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldate	March 28, 2017 +
manufacturer	Intel +
market segment	Workstation + and Server +
max cpu count	1 +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Kaby Lake +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	E3-1275 v6 +
name	Xeon E3-1275 v6 +
package	FCLGA-1151 +
part number	CM8067702870931 + and BX80677E31275V6 +
platform	Greenlow +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 339.00 (€ 305.10, £ 274.59, ¥ 35,028.87) +
s-spec	SR32A +
series	E3-1200 v6 +
smp max ways	1 +
socket	LGA-1151 +
supported memory type	DDR3L-1866 + and DDR4-2400 +
tdp	73 W (73,000 mW, 0.0979 hp, 0.073 kW) +
technology	CMOS +
thread count	8 +
turbo frequency (1 core)	4,200 MHz (4.2 GHz, 4,200,000 kHz) +
turbo frequency (2 cores)	4,100 MHz (4.1 GHz, 4,100,000 kHz) +
turbo frequency (3 cores)	4,100 MHz (4.1 GHz, 4,100,000 kHz) +
turbo frequency (4 cores)	4,000 MHz (4 GHz, 4,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

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NXP

Qualcomm

Renesas

Samsung

Revision as of 02:44, 18 January 2017

Contents

Cache

Memory controller

Expansions

Graphics

Features