Semiconductor & Computer Engineering
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| production end = <!-- production end date, e.g. "January 1, 1985" or "1973" --> | | production end = <!-- production end date, e.g. "January 1, 1985" or "1973" --> | ||
| arch = 4-bit bit-slice | | arch = 4-bit bit-slice | ||
| − | | word = 4 | + | | word = 4 bit |
| proc = <!-- process, e.g. "8 μm" --> | | proc = <!-- process, e.g. "8 μm" --> | ||
| tech = CMOS | | tech = CMOS | ||
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|- | |- | ||
| {{\|4710}} || 16x4-bit RAM Register Stack | | {{\|4710}} || 16x4-bit RAM Register Stack | ||
| + | |- | ||
| + | | {{\|4720}} || 256x1-bit RAM Register Stack | ||
| + | |- | ||
| + | | {{\|4726}} || 256x4-bit RAM Register Stack | ||
| + | |- | ||
| + | | {{\|4735}} || 256x8-bit RAM Register Stack | ||
|} | |} | ||
Latest revision as of 16:18, 12 December 2016
| Fairchild 4700 Family | |
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| |
| Developer | Fairchild Semiconductor |
| Manufacturer | Fairchild Semiconductor |
| Type | microprocessors |
| Production | 1975 |
| Architecture | 4-bit bit-slice |
| Word size | 4 bit 0.5 octets
1 nibbles |
| Technology | CMOS |
| Clock | 2.4576 MHz |
| Package | DIP24, CerDIP24 |
The 4700 Series (officially 4700 Macrologic Series CMOS Family) was a family of 4-bit CMOS multi-chip bit-slice microprocessor designed by Fairchild Semiconductor. The series was introduced in 1975. Around the same time Fairchild introduced the 9400 series which was a similar family using bipolar technology instead.
Contents
2nd Source[edit]
This family was 2nd sourced by Signetics.
Members[edit]
| Family Members | |
|---|---|
| Part | Description |
| 4702 | Bit-rate generator |
| 4703 | Series/Parallel FIFO (Buffer Memory) |
| 4704 | Data Path Switch (DPS) |
| 4705 | Microprocessor "ALRS" (Arithmetic Logic Register Stack) |
| 4706 | Program Stack |
| 4707 | Data Access Register |
| 4708 | Microprogram Sequencer |
| 4710 | 16x4-bit RAM Register Stack |
| 4720 | 256x1-bit RAM Register Stack |
| 4726 | 256x4-bit RAM Register Stack |
| 4735 | 256x8-bit RAM Register Stack |
Architecture[edit]
The individual chips were designed such that they may be chained in cascading manner to support any word size desired (usually multiples of 4). The operations themselves are spread throughout the family, for example 16 register manipulations were provided by the DAR (4707), 8 arithmetic by the ALRS (4705), and 30 shifting/masking/extending operation were provided by the DPS (4704).
There is no actual ISA, it was up to the designer to develop one and assemble the chips accordingly.
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This section requires expansion; you can help adding the missing info. |
See also[edit]
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This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |
| designer | Fairchild Semiconductor + |
| full page name | fairchild/4700 + |
| instance of | microprocessor family + |
| main designer | Fairchild Semiconductor + |
| manufacturer | Fairchild Semiconductor + |
| name | Fairchild 4700 Family + |
| package | DIP24 + and CerDIP24 + |
| technology | CMOS + |
| word size | 4 bit (0.5 octets, 1 nibbles) + |