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'''Cortex-A53''' (formerly '''Apollo''') is a ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A9|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.
 
'''Cortex-A53''' (formerly '''Apollo''') is a ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A9|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance.
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Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
  
 
== Process Technology ==
 
== Process Technology ==

Revision as of 18:58, 3 December 2016

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Cortex-A53 µarch
General Info
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Cortex-A53 (formerly Apollo) is a ultra-high efficiency microarchitecture designed by ARM Holdings as a successor to the Cortex-A9. The Cortex-A53, which implemented the ARMv8 ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on Cortex-A57) in big.LITTLE configuration to achieve better energy/performance.

Note that this microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.

Process Technology

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Architecture

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Die

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All Cortex-A53 Chips

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codenameCortex-A53 +
core count1 +, 2 +, 3 + and 4 +
designerARM Holdings +
first launchedOctober 30, 2012 +
full page namearm holdings/microarchitectures/cortex-a53 +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +, Samsung + and GlobalFoundries +
microarchitecture typeCPU +
nameCortex-A53 +
pipeline stages8 +
process40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) +