From WikiChip
Difference between revisions of "mediatek/helio/mt6795"
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+ | * OpenGL ES 3.0 3D graphic accelerator capable of processing 175M tri/sec and 2,800M pixel/sec @ 700 MHz | ||
+ | * OpenVG 1.1 vector graphics accelerator | ||
== Wireless == | == Wireless == | ||
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| ue cat = 4 | | ue cat = 4 | ||
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+ | == Image == | ||
+ | * Integrated image signal processor supports 20 MP | ||
+ | * Supports image stabilization | ||
+ | * Supports video stabilization | ||
+ | * Supports noise reduction | ||
+ | * Supports lens shading correction | ||
+ | * Supports AE/AWB/AF | ||
+ | * Supports edge enhancement | ||
+ | * Supports face detection and visual tracking | ||
+ | * Hardware JPEG encoder | ||
+ | |||
+ | == Video == | ||
+ | * HEVC decoder 4k2k @ 30fps | ||
+ | * H.264 decoder (30fps/40Mbps) | ||
+ | * Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps) | ||
+ | * MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps) | ||
+ | * DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder (1080p @ 60fps/40Mbps) | ||
+ | * VP8 / VC-1 decoders | ||
+ | * MPEG-4 / H.263 / H.264 / HEVC encoders | ||
+ | |||
+ | == Audio == | ||
+ | * Audio content sampling rates 8kHz to 192kHz | ||
+ | * Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo | ||
+ | * I2S, PCM | ||
+ | * Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM | ||
+ | * Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM | ||
+ | * 7.1 channel MHL output |
Revision as of 04:46, 3 December 2016
Template:mpu Helio X10 (MT6795) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2014. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4.
This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.
Cache
- Main article: Cortex-A53 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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- OpenGL ES 3.0 3D graphic accelerator capable of processing 175M tri/sec and 2,800M pixel/sec @ 700 MHz
- OpenVG 1.1 vector graphics accelerator
Wireless
Wireless Communications | ||||||||||
Cellular | ||||||||||
2G |
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3G |
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4G |
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Image
- Integrated image signal processor supports 20 MP
- Supports image stabilization
- Supports video stabilization
- Supports noise reduction
- Supports lens shading correction
- Supports AE/AWB/AF
- Supports edge enhancement
- Supports face detection and visual tracking
- Hardware JPEG encoder
Video
- HEVC decoder 4k2k @ 30fps
- H.264 decoder (30fps/40Mbps)
- Sorenson H.263/H.263 decoder (1080p @ 60fps/40Mbps)
- MPEG-4 SP/ASP decoder (1080p @ 60fps/40Mbps)
- DIVX4/DIVX5/DIVX6/DIVX HD/XVID decoder (1080p @ 60fps/40Mbps)
- VP8 / VC-1 decoders
- MPEG-4 / H.263 / H.264 / HEVC encoders
Audio
- Audio content sampling rates 8kHz to 192kHz
- Audio content sampling format 8-bit/16-bit/24-bit Mono/Stereo
- I2S, PCM
- Encode: AMR-NB, AMR-WB, AAC, OGG, ADPCM
- Decode: WAV, MP3, MP2, AAC, AMR-NB, AMR-WB, MIDI, Vorbis, APE, AAC-plus v1, AAC-plus v2, FLAC, WMA, ADPCM
- 7.1 channel MHL output
Facts about "Helio X10 (MT6795) - MediaTek"
has 2g support | true + |
has 3g support | true + |
has 4g support | true + |
has csd support | true + |
has dc-hsdpa support | true + |
has e-utran support | true + |
has ecc memory support | false + |
has edge support | true + |
has gprs support | true + |
has hsupa support | true + |
has lte advanced support | true + |
has td-scdma support | true + |
has umts support | true + |
integrated gpu | PowerVR G6200 + |
integrated gpu base frequency | 700 MHz (0.7 GHz, 700,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
max memory bandwidth | 13.9 GiB/s (14,233.6 MiB/s, 14.925 GB/s, 14,925.011 MB/s, 0.0136 TiB/s, 0.0149 TB/s) + |
max memory channels | 2 + |
supported memory type | DDR3-933 + |
user equipment category | 4 + |