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Difference between revisions of "mediatek/helio/mt6795t"
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{{mediatek title|Helio X10 (MT6795T)}} | {{mediatek title|Helio X10 (MT6795T)}} | ||
− | '''Helio X10''' ('''MT6795T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in late-[[2014]]. This SoC, which is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4. | + | {{mpu |
+ | | name = MediaTek Helio X10 | ||
+ | | no image = yes | ||
+ | | image = | ||
+ | | image size = | ||
+ | | caption = | ||
+ | | designer = MediaTek | ||
+ | | designer 2 = ARM Holdings | ||
+ | | manufacturer = TSMC | ||
+ | | model number = Helio X10 | ||
+ | | part number = MT6795T | ||
+ | | market = Mobile | ||
+ | | market 2 = Embedded | ||
+ | | first announced = July 15, 2014 | ||
+ | | first launched = March 27, 2015 | ||
+ | | last order = | ||
+ | | last shipment = | ||
+ | | release price = | ||
+ | |||
+ | | family = Helio | ||
+ | | series = Helio X | ||
+ | | locked = | ||
+ | | frequency = 2,200 MHz | ||
+ | | bus type = AMBA 4 AXI | ||
+ | | bus speed = | ||
+ | | bus rate = | ||
+ | | bus links = | ||
+ | | clock multiplier = | ||
+ | |||
+ | | isa family = ARM | ||
+ | | isa = ARMv8 | ||
+ | | microarch = Cortex-A53 | ||
+ | | platform = | ||
+ | | chipset = | ||
+ | | core name = Cortex-A53 | ||
+ | | core family = | ||
+ | | core model = | ||
+ | | core stepping = | ||
+ | | process = 28 nm | ||
+ | | transistors = | ||
+ | | technology = CMOS | ||
+ | | die area = <!-- XX mm² --> | ||
+ | | die width = | ||
+ | | die length = | ||
+ | | word size = 64 bit | ||
+ | | core count = 8 | ||
+ | | thread count = 8 | ||
+ | | max cpus = 1 | ||
+ | | max memory = 4 GiB | ||
+ | |||
+ | | electrical = Yes | ||
+ | | power = | ||
+ | | v core = 1 V | ||
+ | | v core tolerance = | ||
+ | | v io = 1.8 V | ||
+ | | v io 2 = 2.8 V | ||
+ | | v io 3 = 3.3 V | ||
+ | | sdp = | ||
+ | | tdp = | ||
+ | | tdp typical = | ||
+ | | ctdp down = | ||
+ | | ctdp down frequency = | ||
+ | | ctdp up = | ||
+ | | ctdp up frequency = | ||
+ | | temp min = -20 °C | ||
+ | | temp max = 80 °C | ||
+ | | tjunc min = | ||
+ | | tjunc max = 125 °C | ||
+ | | tcase min = | ||
+ | | tcase max = | ||
+ | | tstorage min = | ||
+ | | tstorage max = | ||
+ | | tambient min = | ||
+ | | tambient max = | ||
+ | |||
+ | | packaging = Yes | ||
+ | | package 0 = MWPOP-1108 | ||
+ | | package 0 type = MWPOP | ||
+ | | package 0 pins = 1108 | ||
+ | | package 0 pitch = 0.4 mm | ||
+ | | package 0 width = 14 mm | ||
+ | | package 0 length = 14 mm | ||
+ | | package 0 height = 0.78 mm | ||
+ | }} | ||
+ | '''Helio X10''' ('''MT6795T''') is a {{arch|64}} [[octa-core]] [[ARM]] [[LTE]] system on a chip designed by [[MediaTek]] and introduced in late-[[2014]]. This SoC, which incorporates eight {{armh|Cortex-A53}} cores and is manufactured on TSMC's [[28 nm process]], operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the {{imgtec|PowerVR G6200}} [[IGP]] operating at 700 MHz. This SoC has a modem supporting [[LTE]] User Equipment (UE) category 4. | ||
+ | |||
+ | This SoC is made of 2 clusters of 4-core each ({{armh|Cortex-A53}}) linked together via a {{armh|CCI-400}}, a {{armh|NEON}} engine, and {{armh|Cortex-R4}} core for the MCU subsystem. |
Revision as of 01:37, 3 December 2016
Template:mpu Helio X10 (MT6795T) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in late-2014. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2.2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the PowerVR G6200 IGP operating at 700 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4.
This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the MCU subsystem.