Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i7/i7-820qm"
| Line 47: | Line 47: | ||
| word size = 64 bit | | word size = 64 bit | ||
| core count = 4 | | core count = 4 | ||
| − | | thread count = | + | | thread count = 8 |
| max cpus = 1 | | max cpus = 1 | ||
| max memory = 8 GiB | | max memory = 8 GiB | ||
Revision as of 19:12, 26 November 2016
Template:mpu Core i7-820QM is a 64-bit x86 quad-core mobile performance microprocessor introduced by Intel late 2009. The processor has a base frequency of 1.73 GHz with a turbo frequency of 3.06 GHz and a TDP of 45 W. This MPU is based on the Clarksfield core (Nehalem microarchitecutre) and is manufactured on Intel's 45 nm process.
Cache
- Main article: Nehalem § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i7-820QM - Intel"
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |