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Difference between revisions of "amd/athlon mp/amsn2800dut4c"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
| − | {{cache | + | {{cache size |
| + | |l1 cache=128 KiB | ||
|l1i cache=64 KiB | |l1i cache=64 KiB | ||
|l1i break=1x64 KiB | |l1i break=1x64 KiB | ||
|l1i desc=2-way set associative | |l1i desc=2-way set associative | ||
| − | |l1i | + | |l1i policy= |
|l1d cache=64 KiB | |l1d cache=64 KiB | ||
|l1d break=1x64 KiB | |l1d break=1x64 KiB | ||
|l1d desc=2-way set associative | |l1d desc=2-way set associative | ||
| − | |l1d | + | |l1d policy= |
|l2 cache=512 KiB | |l2 cache=512 KiB | ||
|l2 break=1x512 KiB | |l2 break=1x512 KiB | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
| − | |l2 | + | |l2 policy= |
| − | |||
| − | |||
| − | |||
| − | |||
}} | }} | ||
Revision as of 15:48, 26 November 2016
Template:mpu Athlon MP 2800+' (OPN AMSN2800DUT4C) based on the last-generation Barton core was a 32-bit x86 multiprocessor developed by AMD and introduced in early 2003 for the server and workstation market. This MPU, which operated at 2.13 GHz with a FSB transfer rate of 266 MT/s (x16 multiplier), was manufactured on a newer 130 nm process.
Cache
- Main article: K7 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This MPU has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents
Datasheets
- AMD Athlon MP Processor Model 10 Data Sheet for Multiprocessor Platforms; Publication # 26426 Rev. C; Issue Date: October 2003.
Others
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 2800+ - AMD"
| has amd smartmp technology | true + |
| has feature | SmartMP Technology +, ACPI +, Halt State + and Stop Grant State + |
| has multiprocessing support | true + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |