Semiconductor & Computer Engineering
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Difference between revisions of "amd/athlon mp/amsn2600dut4c"
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| − | '''Athlon MP 2600+'''' (OPN ''AMSN2600DUT4C'') based on the last-generation {{amd|Barton|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in early [[2003]] for the server and workstation market. This MPU operated at 2 GHz with a FSB transfer rate of 266 MT/s (x15 multiplier), was manufactured on a newer [[130 nm process]]. | + | '''Athlon MP 2600+'''' (OPN ''AMSN2600DUT4C'') based on the last-generation {{amd|Barton|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in early [[2003]] for the server and workstation market. This MPU, which operated at 2 GHz with a FSB transfer rate of 266 MT/s (x15 multiplier), was manufactured on a newer [[130 nm process]]. |
== Cache == | == Cache == | ||
Revision as of 13:00, 17 November 2016
Template:mpu Athlon MP 2600+' (OPN AMSN2600DUT4C) based on the last-generation Barton core was a 32-bit x86 multiprocessor developed by AMD and introduced in early 2003 for the server and workstation market. This MPU, which operated at 2 GHz with a FSB transfer rate of 266 MT/s (x15 multiplier), was manufactured on a newer 130 nm process.
Cache
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
1x64 KiB 2-way set associative |
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
1x512 KiB 16-way set associative |
Graphics
This MPU has no integrated graphics processing unit.
Features
- Advanced Configuration and Power Interface
- Halt State
- Stop Grant State
Documents
Datasheets
- AMD Athlon MP Processor Model 10 Data Sheet for Multiprocessor Platforms; Publication # 26426 Rev. C; Issue Date: October 2003.
Others
- System Considerations for Dual AMD Athlon MP Processors in Tower and 1U Form Factors; Publication # 25325; Rev: B; August 2002.
Facts about "Athlon MP 2600+ - AMD"
| has feature | ACPI +, Halt State + and Stop Grant State + |
| l1d$ description | 2-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |