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Difference between revisions of "intel/xeon e5/e5-2643 v4"
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| s-spec              = SR2P4
 
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| s-spec qs          =  
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| s-spec qs          = QKEZ
 
| cpuid              = 406F1
 
| cpuid              = 406F1
  

Revision as of 00:53, 5 November 2016

Template:mpu The Xeon E5-2643 v4 is a 64-bit hexa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 2S environments (2U square form factor). Operating at 3.4 GHz with a turbo boost frequency of 3.7 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core, write-back)
L1D$ 192 KiB
196,608 B
0.188 MiB
6x32 KiB 8-way set associative (per core, write-back)
L2$ 1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
6x256 KiB 8-way set associative (per core, write-back)
L3$ 20 MiB
20,480 KiB
20,971,520 B
0.0195 GiB
6x3.325 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

Template:mpu expansions

Features

Template:mpu features

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2643_v4&oldid=26970"
Facts about "Xeon E5-2643 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description20-way set associative +
l3$ size20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +