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Difference between revisions of "intel/xeon e5/e5-2699r v4"
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| socket 0 type      = LGA
 
| socket 0 type      = LGA
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}}
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The '''Xeon E5-2699R v4''' is a {{arch|64}} [[docosa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This embedded server MPU is designed for low-power 2S environments. Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
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== Cache ==
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{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
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{{cache info
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|l1i cache=704 KiB
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|l1i break=22x32 KiB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=704 KiB
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|l1d break=22x32 KiB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=5.5 MiB
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|l2 break=22x256 KiB
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|l2 desc=8-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=55 MiB
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|l3 break=22x2.5 MiB
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|l3 desc=20-way set associative
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|l3 extra=(shared, per core, write-back)
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}}
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== Graphics ==
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This microprocessor has no [[integrated graphics processing unit]].
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR4-2400
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| controllers        = 1
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| channels          = 4
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| ecc support        = Yes
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| max bandwidth      = 71.53 GiB/s
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| bandwidth schan    = 17.88 GiB/s
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| bandwidth dchan    = 35.76 GiB/s
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| max memory        = 1,536 GiB
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| pae                = 46 bit
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}}
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== Expansions ==
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{{mpu expansions
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| pcie revision      = 3.0
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| pcie lanes        = 40
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| pcie config        = x4
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| pcie config 1      = x8
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| pcie config 2      = x16
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}}
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== Features ==
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{{mpu features
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| em64t      = Yes
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| nx          = Yes
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| txt        = Yes
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| tsx        = Yes
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| vpro        = Yes
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| ht          = Yes
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| tbt1        =
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| tbt2        = Yes
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| tbmt3      =
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| bpt        =
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| vt-x        = Yes
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| vt-d        = Yes
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| ept        = Yes
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| mmx        = Yes
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| sse        = Yes
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| sse2        = Yes
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| sse3        = Yes
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| ssse3      = Yes
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| sse4.1      = Yes
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| sse4.2      = Yes
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| aes        = Yes
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| pclmul      = Yes
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| avx        = Yes
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| avx2        = Yes
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| bmi        = Yes
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| bmi1        = Yes
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| bmi2        = Yes
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| f16c        = Yes
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| fma3        = Yes
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| mpx        =
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| sgx        =
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| eist        = Yes
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| secure key  = Yes
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| os guard    = Yes
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| intel at    =
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| intel ipt  =
 
}}
 
}}

Revision as of 22:55, 4 November 2016

Template:mpu The Xeon E5-2699R v4 is a 64-bit docosa-core x86 microprocessor introduced by Intel in 2016. This embedded server MPU is designed for low-power 2S environments. Operating at 2.2 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L1D$ 704 KiB
720,896 B
0.688 MiB
22x32 KiB 8-way set associative (per core, write-back)
L2$ 5.5 MiB
5,632 KiB
5,767,168 B
0.00537 GiB
22x256 KiB 8-way set associative (per core, write-back)
L3$ 55 MiB
56,320 KiB
57,671,680 B
0.0537 GiB
22x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

Template:mpu expansions

Features

Template:mpu features

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Facts about "Xeon E5-2699R v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size704 KiB (720,896 B, 0.688 MiB) +
l1i$ description8-way set associative +
l1i$ size704 KiB (720,896 B, 0.688 MiB) +
l2$ description8-way set associative +
l2$ size5.5 MiB (5,632 KiB, 5,767,168 B, 0.00537 GiB) +
l3$ description20-way set associative +
l3$ size55 MiB (56,320 KiB, 57,671,680 B, 0.0537 GiB) +