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Difference between revisions of "amd/duron/d900aut1b"
< amd‎ | duron

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=== Other ===
 
=== Other ===
 
* [[:File:AMD Duron Processor Model 3 Revision Guide (October, 2003).pdf|AMD Duron Processor Model 3 Revision Guide]]; Publication # 23865; Rev: K; Issue Date: October 2003.
 
* [[:File:AMD Duron Processor Model 3 Revision Guide (October, 2003).pdf|AMD Duron Processor Model 3 Revision Guide]]; Publication # 23865; Rev: K; Issue Date: October 2003.
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== Gallery ==
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<gallery>
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File:Ic-photo-AMD-D900AUT1B-(Duron).png
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</gallery>

Revision as of 01:37, 26 October 2016

Template:mpu Duron 900 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 900 MHz with a bus capable of 200 MT/s with a TDP of 39.5 W.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State

Documents

DataSheet

Other

Gallery

  • Ic-photo-AMD-D900AUT1B-(Duron).png
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/duron/d900aut1b&oldid=26236"
Facts about "Duron 900 (Spitfire) - AMD"
RDF feed
has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +