Difference between revisions of "exponential technology/x704/466"

Revision as of 23:56, 20 September 2016

Template:mpu X704 466 MHz was a PowerPC-compatible microprocessor operating at 466 MHz announced in January 1997 by Exponential Technology. The company folded before the model ever reaching market (See X704 § History).

Main article: X704 § Cache

Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.

This SoC has no integrated graphics processing unit.

Fully PowerPC 60x-compatible architecture
IEEE 1149.1-compliant JTAG test access port
IEEE 754-compliant single-precision and double-precision arithmetic
Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
Support for all PowerPC cache operations
Support for PowerEndian and BigEndian modes

@@ Line 77: / Line 77: @@
 == Cache ==
 {{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}}
-Level 3 can be provided externally with cache size of 512 KB to 2 MB.
+Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.
 {{cache info
-|l1i cache=2 KB
+|l1i cache=2 KiB
-|l1i break=1x2 KB
+|l1i break=1x2 KiB
 |l1i desc=direct mapped
 |l1i extra=
-|l1d cache=2 KB
+|l1d cache=2 KiB
-|l1d break=1x2 KB
+|l1d break=1x2 KiB
 |l1d desc=direct mapped
 |l1d extra=
-|l2 cache=32 KB
+|l2 cache=32 KiB
-|l2 break=1x32 KB
+|l2 break=1x32 KiB
 |l2 desc=8-way set associative
 |l2 extra=