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Difference between revisions of "amd/k6-iii+/amd-k6-iii+-450acz"
< amd‎ | k6-iii+

Line 40: Line 40:
 
| core stepping 4    = 3
 
| core stepping 4    = 3
 
| process            = 0.18 µm
 
| process            = 0.18 µm
| transistors        = 21,300,000
+
| transistors        = 21,400,000
 
| technology          = CMOS
 
| technology          = CMOS
 
| die area            = <!-- XX mm² -->
 
| die area            = <!-- XX mm² -->
Line 81: Line 81:
 
| socket 0 2 type    = PGA-321
 
| socket 0 2 type    = PGA-321
 
}}
 
}}
'''AMD-K6-III+/400ACZ''' is a {{arch|32}} [[x86]] desktop microprocessor designed by [[AMD]] and introduced in early [[1999]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4 with a maximum power dissipation rating of 16 W.
+
'''AMD-K6-III+/400ACZ''' is a {{arch|32}} [[x86]] desktop microprocessor designed by [[AMD]] and introduced in early [[1999]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4 with a maximum power dissipation rating of 16 W and a typical rating of 12.6 W.
  
 
== Cache ==
 
== Cache ==

Revision as of 18:21, 9 September 2016

Template:mpu AMD-K6-III+/400ACZ is a 32-bit x86 desktop microprocessor designed by AMD and introduced in early 1999. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 400 MHz with a bus of 100 MHz and a multiplier of 4 with a maximum power dissipation rating of 16 W and a typical rating of 12.6 W.

Cache

Main article: K6-III § Cache

L3$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L3$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative
L1D$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative
L2$ 256 KB
"KB" is not declared as a valid unit of measurement for this property.
1x256 4-way set associative (shared)

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state
  • Halt state
l1d$ description2-way set associative +
l1i$ description2-way set associative +
l2$ description4-way set associative +