Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6-iii/amd-k6-iii-333afr"
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Revision as of 05:56, 8 September 2016
Template:mpu K6-III/333AFR is a 32-bit x86 desktop microprocessor designed by AMD and introduced in early 1999. This MPU which was manufactured on a 0.25 µm process, based on K6-III microarchitecture, operated at 333 MHz with a bus of 95 MHz. While default to a 95 MHz bus (Super 7), this model can also operate at the old Socket 7 bus speed of 66 MHz (multiplier of 5).
Cache
- Main article: K6-III § Cache
L3$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L3$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
| L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
| L2$ | 256 KB "KB" is not declared as a valid unit of measurement for this property. |
1x256 4-way set associative (shared) |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
- Halt state
Facts about "AMD-K6-III/333AFR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |
| l2$ description | 4-way set associative + |