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Difference between revisions of "intel/process-architecture-optimization"
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Under the Process-Architecture-Optimization Model: | Under the Process-Architecture-Optimization Model: | ||
| − | * '''Process''' - With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and a generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their {{intel|microarchitectures|previous}} [[microarchitecture]] to the new process which inherently yielded better performance and energy saving. During a | + | * '''Process''' - With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and a generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their {{intel|microarchitectures|previous}} [[microarchitecture]] to the new process which inherently yielded better performance and energy saving. During a "process", usually just a few features and improvements and new instructions are introduced. |
| − | * '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. | + | * '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New instructions are often added during this cycle stage. |
* '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additional the process itself enjoys various refinements it matures. | * '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additional the process itself enjoys various refinements it matures. | ||
Revision as of 02:35, 3 August 2016
Process-Architecture-Optimization is a development model introduced by Intel for their mainstream microprocessors in 2016 following the phase-out of their Tick-Tock model. The change is a result of the increase in cost and complexity of advancing lithography processes in the past decade. Under the new model the amount of time utilized for any given process technology is lengthen.
Under the Process-Architecture-Optimization Model:
- Process - With each process, Intel advances their manufacturing process technology in line with Moore's Law. Each new process introduces higher transistor density and a generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their previous microarchitecture to the new process which inherently yielded better performance and energy saving. During a "process", usually just a few features and improvements and new instructions are introduced.
- Architecture - With each architecture, Intel uses the their latest manufacturing process technology from their "process" to manufacture a newly designed microarchitecture. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New instructions are often added during this cycle stage.
- Optimization - With each optimization, Intel improves upon their previous microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additional the process itself enjoys various refinements it matures.
Schedule
| Intel Tick-Tock Schedule | |||
|---|---|---|---|
| Cycle | Process | Introduction | Microarchitecture |
| Process | 14 nm | 2014 | Broadwell |
| Architecture | 14 nm | 2015 | Skylake |
| Optimization | 14 nm | 2016 | Kaby Lake |
| Optimization | 14 nm | 2017 | Coffee Lake |
| Process | 10 nm | 2017 | Cannonlake |
| Architecture | 10 nm | 2018 | Icelake |
| Optimization | 10 nm | 2019 | Tigerlake |
Facts about "Process-Architecture-Optimization (PAO) - Intel"
| instance of | development model + |
| name | Process-Architecture-Optimization + |