From WikiChip
Difference between revisions of "intel/xeon e7/e7-4807"
(Created page with "{{intel title|Xeon E7-4807}} {{mpu | name = Xeon E7-4807 | no image = Yes | image = | image size = | caption =...") |
|||
| Line 78: | Line 78: | ||
| socket 0 type = LGA | | socket 0 type = LGA | ||
}} | }} | ||
| − | '''Xeon E7-4807''' is a {{arch|64}} [[x86]] data center microprocessor that supports up to 4 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.86 GHz with 95 W TDP but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory. | + | '''Xeon E7-4807''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 4 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.86 GHz with 95 W TDP but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory. |
| + | |||
| + | == Cache == | ||
| + | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
| + | {{cache info | ||
| + | |l1i cache=192 KB | ||
| + | |l1i break=6x32 KB | ||
| + | |l1i desc=4-way set associative | ||
| + | |l1i extra=(per core) | ||
| + | |l1d cache=192 KB | ||
| + | |l1d break=6x32 KB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d extra=(per core) | ||
| + | |l2 cache=1.5 MB | ||
| + | |l2 break=6x256 KB | ||
| + | |l2 desc=8-way set associative | ||
| + | |l2 extra=(per core) | ||
| + | |l3 cache=18 MB | ||
| + | |l3 break= | ||
| + | |l3 desc=16-way set associative | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Memory controller == | ||
| + | {{integrated memory controller | ||
| + | | type = DDR3-800 | ||
| + | | controllers = 1 | ||
| + | | channels = 4 | ||
| + | | ecc support = Yes | ||
| + | | max bandwidth = | ||
| + | | bandwidth schan = | ||
| + | | bandwidth dchan = | ||
| + | | max memory = 2048 GB | ||
| + | }} | ||
| + | |||
| + | == Features == | ||
| + | {{mpu features | ||
| + | | em64t = Yes | ||
| + | | nx = Yes | ||
| + | | txt = Yes | ||
| + | | tsx = | ||
| + | | vpro = | ||
| + | | ht = Yes | ||
| + | | tbt1 = | ||
| + | | tbt2 = | ||
| + | | bpt = | ||
| + | | vt-x = Yes | ||
| + | | vt-d = yes | ||
| + | | ept = Yes | ||
| + | | mmx = Yes | ||
| + | | sse = Yes | ||
| + | | sse2 = Yes | ||
| + | | sse3 = Yes | ||
| + | | ssse3 = Yes | ||
| + | | sse4.1 = Yes | ||
| + | | sse4.2 = Yes | ||
| + | | aes = Yes | ||
| + | | pclmul = | ||
| + | | avx = | ||
| + | | avx2 = | ||
| + | | bmi = | ||
| + | | bmi1 = | ||
| + | | bmi2 = | ||
| + | | f16c = | ||
| + | | fma3 = | ||
| + | | mpx = | ||
| + | | sgx = | ||
| + | | eist = Yes | ||
| + | | secure key = | ||
| + | | os guard = | ||
| + | | intel at = | ||
| + | }} | ||
Revision as of 23:01, 12 June 2016
Template:mpu Xeon E7-4807 is a 64-bit hexa-core x86 data center microprocessor that supports up to 4 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.86 GHz with 95 W TDP but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 2 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 192 KB "KB" is not declared as a valid unit of measurement for this property. |
6x32 KB 4-way set associative (per core) |
| L1D$ | 192 KB "KB" is not declared as a valid unit of measurement for this property. |
6x32 KB 8-way set associative (per core) |
| L2$ | 1.5 MB "MB" is not declared as a valid unit of measurement for this property. |
6x256 KB 8-way set associative (per core) |
| L3$ | 18 MB "MB" is not declared as a valid unit of measurement for this property. |
16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3-800 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max memory | 2048 GB |
Features
Facts about "Xeon E7-4807 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E7-4807 - Intel#package + |
| base frequency | 1,866.66 MHz (1.867 GHz, 1,866,660 kHz) + |
| bus rate | 4,800 MT/s (4.8 GT/s, 4,800,000 kT/s) + |
| bus type | QPI + |
| chipset | Boxboro + |
| clock multiplier | 14 + |
| core count | 6 + |
| core family | 6 + |
| core model | 47 + |
| core name | Westmere EX + |
| core stepping | A2 + |
| core voltage | 1.35 V (13.5 dV, 135 cV, 1,350 mV) + |
| cpuid | 206F2 + |
| designer | Intel + |
| die area | 513 mm² (0.795 in², 5.13 cm², 513,000,000 µm²) + |
| family | Xeon E7 + |
| first announced | April 5, 2011 + |
| first launched | April 5, 2011 + |
| full page name | intel/xeon e7/e7-4807 + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
| has intel enhanced speedstep technology | true + |
| has intel trusted execution technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
| last order | August 21, 2015 + |
| last shipment | February 5, 2016 + |
| ldate | April 5, 2011 + |
| manufacturer | Intel + |
| market segment | Server + |
| max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
| max cpu count | 4 + |
| max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
| max memory bandwidth | 23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) + |
| max memory channels | 4 + |
| max storage temperature | 358.15 K (85 °C, 185 °F, 644.67 °R) + |
| microarchitecture | Westmere + |
| min case temperature | 278.15 K (5 °C, 41 °F, 500.67 °R) + |
| min storage temperature | 233.15 K (-40 °C, -40 °F, 419.67 °R) + |
| model number | E7-4807 + |
| name | Xeon E7-4807 + |
| package | FCLGA-8 + |
| part number | AT80615006432AB + |
| platform | Boxboro + |
| process | 32 nm (0.032 μm, 3.2e-5 mm) + |
| release price | $ 890.00 (€ 801.00, £ 720.90, ¥ 91,963.70) + |
| s-spec | SLC3L + |
| series | E7-4800 + |
| smp max ways | 4 + |
| supported memory type | DDR3-800 + |
| tdp | 95 W (95,000 mW, 0.127 hp, 0.095 kW) + |
| technology | CMOS + |
| thread count | 12 + |
| transistor count | 2,600,000,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |