Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/microarchitectures/skylake (client)"
(+tech) |
(changes from broadwell) |
||
| Line 34: | Line 34: | ||
{{main|intel/microarchitectures/broadwell#Technology|l1=Broadwell § Technology}} | {{main|intel/microarchitectures/broadwell#Technology|l1=Broadwell § Technology}} | ||
Skylake uses the same [[14 nm process]] used for the Broadwell microarchitecture. | Skylake uses the same [[14 nm process]] used for the Broadwell microarchitecture. | ||
| + | |||
| + | == Architecture == | ||
| + | Overall Skylake builds upon Intel's previous microarchitecture, {{\\|Broadwell}}, but includes a more beefed up front end, more optimized execution engine, and numerous number of smaller enhancements including | ||
| + | |||
| + | === Key changes from {{\\|Broadwell}} === | ||
| + | * Front End | ||
| + | ** Larger legacy pipeline delivery (5 µOPs, up from 4) | ||
| + | ** Larger IDQ delivery (6 µOPs, up from 4) | ||
| + | ** 2.28x larger allocation queue (64/thread, up from 28/thread) | ||
| + | ** Improved [[branch prediction unit]] | ||
| + | * Execution Engine | ||
| + | ** Larger [[re-order buffer]] (224 entries, up from 192) | ||
| + | ** Larger scheduler (97 entries, up from 60) | ||
| + | *** Larger Integer Register File (180 entries, up from 160) | ||
| + | ** Larger store buffer (56 entries, up from 42) | ||
| + | * Memory | ||
| + | ** [[L2$]] was changed from 8-way to 4-way set associative | ||
| + | * TLBs | ||
| + | ** ITLB | ||
| + | *** 4KB page translations was changed from 4-way to 8-way associative | ||
| + | ** STLB | ||
| + | *** 4KB+2M page translations was changed from 6-way to 12-way associative | ||
Revision as of 08:18, 2 May 2016
| Edit Values | |
| Skylake µarch | |
| General Info |
Skylake (SKL) is Intel's microarchitecture using 14 nm process for mainstream desktops, servers, and mobiles. Skylake became the successor to the short-lived Broadwell which experienced severe delays.
For desktop and mobile, Skylake is branded as 6th Generation Intel Core processors. For server class processors, Intel branded it as Xeon E3 v5, Xeon E5 v5, and Xeon E7 v5.
Codenames
| Core | Abbrev | Target |
|---|---|---|
| Skylake Y | SKL-Y | 2-in-1s detachable, tablets, and computer sticks |
| Skylake U | SKL-U | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
| Skylake H | SKL-H | Ultimate mobile performance, mobile workstations |
| Skylake S | SKL-S | Desktop performance to value, AiOs, and minis |
Technology
- Main article: Broadwell § Technology
Skylake uses the same 14 nm process used for the Broadwell microarchitecture.
Architecture
Overall Skylake builds upon Intel's previous microarchitecture, Broadwell, but includes a more beefed up front end, more optimized execution engine, and numerous number of smaller enhancements including
Key changes from Broadwell
- Front End
- Larger legacy pipeline delivery (5 µOPs, up from 4)
- Larger IDQ delivery (6 µOPs, up from 4)
- 2.28x larger allocation queue (64/thread, up from 28/thread)
- Improved branch prediction unit
- Execution Engine
- Larger re-order buffer (224 entries, up from 192)
- Larger scheduler (97 entries, up from 60)
- Larger Integer Register File (180 entries, up from 160)
- Larger store buffer (56 entries, up from 42)
- Memory
- L2$ was changed from 8-way to 4-way set associative
- TLBs
- ITLB
- 4KB page translations was changed from 4-way to 8-way associative
- STLB
- 4KB+2M page translations was changed from 6-way to 12-way associative
- ITLB