Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/atom x5/x5-z8500"
(→Memory controller) |
m (→Cache) |
||
| Line 66: | Line 66: | ||
== Cache == | == Cache == | ||
| + | {{main|intel/microarchitectures/airmont#Memory_Hierarchy|l1=Airmont's Cache}} | ||
{{cache info | {{cache info | ||
|l1i cache=128 KB | |l1i cache=128 KB | ||
| Line 75: | Line 76: | ||
|l1d desc=6-way set associative | |l1d desc=6-way set associative | ||
|l1d extra=(per core) | |l1d extra=(per core) | ||
| − | |l2 cache= | + | |l2 cache=2 MB |
|l2 break=2x1 MB | |l2 break=2x1 MB | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
| − | |l2 extra=(per | + | |l2 extra=(per 2 cores) |
|l3 cache=0 KB | |l3 cache=0 KB | ||
|l3 desc=No L3$ | |l3 desc=No L3$ | ||
Revision as of 09:39, 10 April 2016
Template:mpu The Atom x5-Z8500 is a 64-bit quad-core system on a chip introduce by Intel in early 2015. This ultra-low power SoC has a scenario design power of 2 W and operates at a base frequency of 1.44 GHz with a burst up to 2.24 GHz and supports up to 8 GB of memory. This chip incorporates the HD Graphics (Cherry Trail) GPU.
Cache
- Main article: Airmont's Cache
| Cache Info [Edit Values] | ||
| L1I$ | 128 KB "KB" is not declared as a valid unit of measurement for this property. |
4x32 KB 8-way set associative (per core) |
| L1D$ | 96 KB "KB" is not declared as a valid unit of measurement for this property. |
4x24 KB 6-way set associative (per core) |
| L2$ | 2 MB "MB" is not declared as a valid unit of measurement for this property. |
2x1 MB 16-way set associative (per 2 cores) |
| L3$ | 0 KB "KB" is not declared as a valid unit of measurement for this property. |
No L3$ |
Memory controller
| Integrated Memory Controller | |
| Type | DDR3L-RS 1600, LPDDR3 1600 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Bandwidth (single) | 12,800 MB/s |
| Bandwidth (dual) | 25,600 MB/s |
| Max memory | 8,192 MB |
Graphics
| Integrated Graphic Information | |
| GPU | HD Graphics (Cherry Trail) |
| Execution Units | 12 |
| Displays | 3 |
| Frequency | 200 MHz 0.2 GHz
200,000 KHz |
| Max frequency | 600 MHz 0.6 GHz
600,000 KHz |
| Max memory | 8 GB "GB" is not declared as a valid unit of measurement for this property.
|
| Output | Embedded DisplayPort, HDMI |
| DirectX | 11.1 |
| OpenGL | 4.3 |
| OpenCL | 1.2 |
| OpenGL ES | 3.0 |
| DVI | 1.4b |
| HDMI | 1.4b |
| DVI | 1.4b |
| Vulkan | 1.0 |
| DP | 1.1a |
| eDP | 1.3 |
| Max HDMI Res | 3840x2160 @60 |
| Max DVI Res | 3840x2160 @60 Hz |
| Max DSI Res | 2560x1600 @60 Hz |
| Max DP Res | 2560x1600 @60 |
| Max eDP Res | 2560x1600 @60 Hz |
- Video decode hardware acceleration including support for H.263, MPEG4, H.264, H.265 (HEVC), VP8, VP9, MVC, MPEG2, VC1, JPEG.
- Video encode hardware acceleration including support for H.264, H.263, VP8, MVC, JPEG.
- Four planes available per pipe - 1x Primary, 2x Video Sprite & 1x Cursor.
- Two dedicated digital Display Serial Interface PHYs implementing MIPI-DSI support.
Expansions
Features
Storage
- SD Card support (x1 SDR104)
- SDIO support (x1 SDR104)
- eMMC support (4.51)
Audio
- Low Power Engine (3 I2S ports)
Package
| Property | Value |
|---|---|
| Type | 17x17mm Type 4 |
| IO count | 628 |
| Ball count | 1380 |
| Ball pitch | 0.4mm |
| Z-height | 0.937mm |
Facts about "Atom x5-Z8500 - Intel"
| has feature | integrated gpu +, SD Card support +, SDIO support +, eMMC support + and Low Power Engine + |
| integrated gpu | HD Graphics (Cherry Trail) + |
| integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
| integrated gpu max frequency | 600 MHz (0.6 GHz, 600,000 KHz) + |
| l1d$ description | 6-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 16-way set associative + |
| l3$ description | No L3$ + |