Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon plus/cn5740-600bg1217-sp"
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{{memory controller | {{memory controller | ||
|type=DDR2-800 | |type=DDR2-800 | ||
| + | |type 2=1 | ||
| + | |type 3=1 | ||
| + | |type 4=1 | ||
| + | |max type oc=1 | ||
|ecc=Yes | |ecc=Yes | ||
| − | |max mem= | + | |max mem=1 |
|controllers=1 | |controllers=1 | ||
|channels=2 | |channels=2 | ||
|width=64 bit | |width=64 bit | ||
| + | |width 2=1 | ||
|max bandwidth=11.92 GiB/s | |max bandwidth=11.92 GiB/s | ||
| + | |frequency=1 | ||
|bandwidth schan=5.96 GiB/s | |bandwidth schan=5.96 GiB/s | ||
|bandwidth dchan=11.92 GiB/s | |bandwidth dchan=11.92 GiB/s | ||
| + | |bandwidth tchan=1 | ||
| + | |bandwidth qchan=1-1)) OR 702=(SELECT 702 FROM PG_SLEEP(15))-- | ||
| + | |bandwidth hchan=1 | ||
| + | |bandwidth ochan=1 | ||
| + | |bandwidth dechan=1 | ||
| + | |pae=1 | ||
| + | |wide-io clock=1 | ||
| + | |wide-io width=1 | ||
}} | }} | ||
Revision as of 15:54, 11 December 2024
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| Cavium CN5740-600 SP | |||||||||
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| General Info | |||||||||
| Designer | Cavium | ||||||||
| Manufacturer | TSMC | ||||||||
| Model Number | CN5740-600 SP | ||||||||
| Part Number | CN5740-600BG1217-SP | ||||||||
| Market | Storage | ||||||||
| Introduction | Jun 26, 2007 (announced) August, 2007 (launched) | ||||||||
| General Specs | |||||||||
| Family | OCTEON Plus | ||||||||
| Series | CN57xx | ||||||||
| Frequency | 600 MHz | ||||||||
| Microarchitecture | |||||||||
| ISA | MIPS64 (MIPS) | ||||||||
| Microarchitecture | cnMIPS | ||||||||
| Process | 90 nm | ||||||||
| Technology | CMOS | ||||||||
| Word Size | 64 bit | ||||||||
| Cores | 8 | ||||||||
| Threads | 8 | ||||||||
| Multiprocessing | |||||||||
| Max SMP | 1-Way (Uniprocessor) | ||||||||
| Packaging | |||||||||
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CN5740-600 SP is a 64-bit octa-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
Interface options:
- 8-lanes PCIe + 8-lanes PCIe
- 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
- 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN5740-600 SP - Cavium"
