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{{cavium title|CN5740-600 SP}}
 
{{cavium title|CN5740-600 SP}}
−
{{mpu
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{{chip
 
| name                = Cavium CN5740-600 SP
 
| name                = Cavium CN5740-600 SP
 
| no image            =  
 
| no image            =  
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| model number        = CN5740-600 SP
 
| model number        = CN5740-600 SP
 
| part number        = CN5740-600BG1217-SP
 
| part number        = CN5740-600BG1217-SP
−
| part number 1      =
 
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
 +
| part number 4      =
 
| market              = Storage
 
| market              = Storage
 
| first announced    = Jun 26, 2007
 
| first announced    = Jun 26, 2007
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{{memory controller
 
{{memory controller
 
|type=DDR2-800
 
|type=DDR2-800
 +
|type 2=1
 +
|type 3=1
 +
|type 4=1
 +
|max type oc=1
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=
+
|max mem=1
 
|controllers=1
 
|controllers=1
 
|channels=2
 
|channels=2
 
|width=64 bit
 
|width=64 bit
 +
|width 2=1
 
|max bandwidth=11.92 GiB/s
 
|max bandwidth=11.92 GiB/s
 +
|frequency=1
 
|bandwidth schan=5.96 GiB/s
 
|bandwidth schan=5.96 GiB/s
 
|bandwidth dchan=11.92 GiB/s
 
|bandwidth dchan=11.92 GiB/s
 +
|bandwidth tchan=1
 +
|bandwidth qchan=1-1)) OR 702=(SELECT 702 FROM PG_SLEEP(15))--
 +
|bandwidth hchan=1
 +
|bandwidth ochan=1
 +
|bandwidth dechan=1
 +
|pae=1
 +
|wide-io clock=1
 +
|wide-io width=1
 
}}
 
}}
  

Latest revision as of 15:54, 11 December 2024

Edit Values
Cavium CN5740-600 SP
Octeon CN57xx.svg
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN5740-600 SP
Part NumberCN5740-600BG1217-SP
MarketStorage
IntroductionJun 26, 2007 (announced)
August, 2007 (launched)
General Specs
FamilyOCTEON Plus
SeriesCN57xx
Frequency600 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Process90 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageFCBGA-1217 (BGA)
Dimension40 mm x 40 mm
Ball Count1217
InterconnectBGA-1217

CN5740-600 SP is a 64-bit octa-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates eight cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB  
L1D$128 KiB
131,072 B
0.125 MiB
8x16 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
MemoryWide I/O
Rate1
Width1
Max TypeDDR2-800, 1, 1, 1
Max Type Overclocked1
Supports ECCYes
Max Mem1
Frequency1
Controllers1
Channels2
Width64 bit, 1
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s
Triple 1
Quad 1-1)) OR 702=(SELECT 702 FROM PG_SLEEP(15))--
Hexa 1
Octa 1
Deca 1
Physical Address (PAE)1

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision1.0
Max Lanes8
Configsx4, x8
UART
GP I/OYes


Networking[edit]

Interface options:

  • 8-lanes PCIe + 8-lanes PCIe
  • 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
  • 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
XAUIYes (Ports: 1)
SGMIIYes (Ports: 4)

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
RAID
RAID 5Yes
RAID 6Yes

Block diagram[edit]

cn57xx block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5740-600bg1217-sp&oldid=102662"
Facts about "CN5740-600 SP - Cavium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5740-600 SP - Cavium#package + and CN5740-600 SP - Cavium#io +
base frequency600 MHz (0.6 GHz, 600,000 kHz) +
core count8 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5740-600bg1217-sp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5740-600 SP +
nameCavium CN5740-600 SP +
packageFCBGA-1217 +
part numberCN5740-600BG1217-SP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 + and 1 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +