From WikiChip
Difference between revisions of "intel/xeon e5/e5-2697a v4"
< intel‎ | xeon e5

(Created page with "{{intel title|Xeon E5-2697A v4}} {{mpu | name = Xeon E5-2697A v4 | no image = Yes | image = | image size = | caption...")
 
 
(16 intermediate revisions by 4 users not shown)
Line 1: Line 1:
 
{{intel title|Xeon E5-2697A v4}}
 
{{intel title|Xeon E5-2697A v4}}
−
{{mpu
+
{{chip
−
| name               = Xeon E5-2697A v4
+
|name=Xeon E5-2697A v4
−
| no image           = Yes
+
|no image=Yes
−
| image              =
+
|designer=Intel
−
| image size          =
+
|manufacturer=Intel
−
| caption            =
+
|model number=E5-2697A v4
−
| designer           = Intel
+
|part number=CM8066002645900
−
| manufacturer       = Intel
+
|s-spec=SR2K1
−
| model number       = E5-2697A v4
+
|s-spec qs=QK7S
−
| part number         = CM8066002645900
+
|market=Server
−
| part number 1      =  
+
|first announced=June 20, 2016
−
| part number 2      =
+
|first launched=June 20, 2016
−
| part number 3      =  
+
|release price=$2891.00
−
| market             = Server
+
|family=Xeon E5
−
| first announced     = June 20, 2016
+
|series=E5-2000
−
| first launched     = June 20, 2016
+
|locked=Yes
−
| last order          =  
+
|frequency=2,600 MHz
−
| last shipment      =  
+
|turbo frequency1=3,600 MHz
−
| release price      = $2891.00
+
|turbo frequency2=3,600 MHz
 +
|turbo frequency3=3,400 MHz
 +
|turbo frequency4=3,300 MHz
 +
|turbo frequency5=3,200 MHz
 +
|turbo frequency6=3,100 MHz
 +
|turbo frequency7=3,100 MHz
 +
|turbo frequency8=3,100 MHz
 +
|turbo frequency9=3,100 MHz
 +
|turbo frequency10=3,100 MHz
 +
|turbo frequency11=3,100 MHz
 +
|turbo frequency12=3,100 MHz
 +
|turbo frequency13=3,100 MHz
 +
|turbo frequency14=3,100 MHz
 +
|turbo frequency15=3,100 MHz
 +
|turbo frequency16=3,100 MHz
 +
|turbo frequency=Yes
 +
|bus type=QPI
 +
|bus speed=4,800 MHz
 +
|bus links=2
 +
|bus rate=9.6 GT/s
 +
|clock multiplier=26
 +
|cpuid=406F1
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Broadwell
 +
|platform=Grantley EP 2S
 +
|chipset=C610 Series
 +
|core name=Broadwell EP
 +
|core family=6
 +
|core model=4F
 +
|core stepping=B0
 +
|process=14 nm
 +
|transistors=7,200,000,000
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=16
 +
|thread count=32
 +
|max memory=1,536 GiB
 +
|max cpus=2
 +
|v core=1.82 V
 +
|v io=1.2 V
 +
|v io tolerance=3%
 +
|tdp=145 W
 +
|tcase min=0 °C
 +
|tcase max=78 °C
 +
|tstorage min=-25 °C
 +
|tstorage max=125 °C
 +
|die size=456.12 mm²
 +
|packaging=Yes
 +
|package 0=FCLGA-2011-v3
 +
|package 0 type=FCLGA
 +
|package 0 pins=2011
 +
|package 0 pitch=0.8814 mm
 +
|package 0 width=52.5 mm
 +
|package 0 length=45.0 mm
 +
|package 0 height=5.316 mm
 +
|socket 0=LGA-2011-v3
 +
|socket 0 type=LGA
 +
}}
 +
The '''Xeon E5-2697A v4''' is a {{arch|64}} [[hexadeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.6 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
  
−
| family              = Xeon E5
+
== Cache ==
−
| series              = E5-2000
+
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
−
| locked              = Yes
+
{{cache info
−
| frequency          = 2,600 MHz
+
|l1i cache=512 KiB
−
| turbo frequency    = Yes
+
|l1i break=16x32 KiB
−
| turbo frequency1    = 3,600 MHz
+
|l1i desc=8-way set associative
−
| turbo frequency2    =  
+
|l1i extra=(per core, write-back)
−
| bus type            = QPI
+
|l1d cache=512 KiB
−
| bus speed          = 4,800 MHz
+
|l1d break=16x32 KiB
−
| bus rate            = 9.6 GT/s
+
|l1d desc=8-way set associative
−
| bus links          = 2
+
|l1d extra=(per core, write-back)
−
| clock multiplier    = 26
+
|l2 cache=4 MiB
−
| s-spec              = SR2K1
+
|l2 break=16x256 KiB
−
| s-spec es          =  
+
|l2 desc=8-way set associative
−
| s-spec qs          =
+
|l2 extra=(per core, write-back)
−
| cpuid              = 406F1
+
|l3 cache=40 MiB
 +
|l3 break=16x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}
  
−
| microarch          = Broadwell
+
== Graphics ==
−
| platform            = Grantley EP 2S
+
This microprocessor has no [[integrated graphics processing unit]].
−
| chipset            = C610 Series
 
−
| core name          = Broadwell EP
 
−
| core family        = 6
 
−
| core model          = 15
 
−
| core stepping      = B0
 
−
| process            = 14 nm
 
−
| transistors        = 7,200,000,000
 
−
| technology          = CMOS
 
−
| die size            = 456.12 mm²
 
−
| word size          = 64 bit
 
−
| core count          = 16
 
−
| thread count        = 32
 
−
| max cpus            = 2
 
−
| max memory          = 1,536 GiB
 
  
−
| electrical          = Yes
+
== Memory controller ==
−
| v core              = 1.82 V
+
{{integrated memory controller
−
| v core tolerance    =  
+
| type              = DDR4-2400
−
| v io                = 1.2 V
+
| controllers        = 1
−
| v io tolerance      = 3%
+
| channels           = 4
−
| sdp                =  
+
| ecc support        = Yes
−
| tdp                = 145 W
+
| max bandwidth      = 71.53 GiB/s
−
| ctdp down           =  
+
| bandwidth schan    = 17.88 GiB/s
−
| ctdp down frequency =  
+
| bandwidth dchan    = 35.76 GiB/s
−
| ctdp up            =  
+
| max memory        = 1,536 GiB
−
| ctdp up frequency  =  
+
| pae                = 46 bit
−
| tjunc min          =  
+
}}
−
| tjunc max           =  
 
−
| tcase min          = 0 °C
 
−
| tcase max          = 78 °C
 
−
| tstorage min        = -25 °C
 
−
| tstorage max        = 125 °C
 
  
−
| packaging          = Yes
+
== Expansions ==
−
| package 0          = FCLGA-2011-v3
+
{{expansions
−
| package 0 type     = FCLGA
+
| pcie revision      = 3.0
−
| package 0 pins     = 2011
+
| pcie lanes        = 40
−
| package 0 pitch    = 0.8814 mm
+
| pcie config        = x4
−
| package 0 width    = 52.5 mm
+
| pcie config 1      = x8
−
| package 0 length    = 45.0 mm
+
| pcie config 2      = x16
−
| package 0 height   = 5.316 mm
+
}}
−
| socket 0            = LGA-2011-v3
+
 
−
| socket 0 type      = LGA
+
== Features ==
 +
{{x86 features
 +
| em64t      = Yes
 +
| nx          = Yes
 +
| txt        = Yes
 +
| tsx        = Yes
 +
| vpro        = Yes
 +
| ht          = Yes
 +
| tbt1        =
 +
| tbt2        = Yes
 +
| tbmt3      =
 +
| bpt        =  
 +
| vt-x        = Yes
 +
| vt-d        = Yes
 +
| ept        = Yes
 +
| mmx        = Yes
 +
| sse        = Yes
 +
| sse2        = Yes
 +
| sse3        = Yes
 +
| ssse3      = Yes
 +
| sse4.1      = Yes
 +
| sse4.2     = Yes
 +
| aes        = Yes
 +
| pclmul     = Yes
 +
| avx        = Yes
 +
| avx2        = Yes
 +
| bmi        = Yes
 +
| bmi1        = Yes
 +
| bmi2        = Yes
 +
| f16c        = Yes
 +
| fma3        = Yes
 +
| mpx        =
 +
| sgx        =  
 +
| eist        = Yes
 +
| secure key  = Yes
 +
| os guard   = Yes
 +
| intel at    =  
 +
| intel ipt  =  
 
}}
 
}}
−
The '''Xeon E5-2697A v4''' is a {{arch|64}} [[hexadeca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.6 GHz with a {{intel|turbo boost}} frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 

Latest revision as of 20:46, 2 February 2024

Edit Values
Xeon E5-2697A v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2697A v4
Part NumberCM8066002645900
S-SpecSR2K1
QK7S (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
Release Price$2891.00
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency2,600 MHz
Turbo FrequencyYes
Turbo Frequency3,600 MHz (1 core),
3,600 MHz (2 cores),
3,400 MHz (3 cores),
3,300 MHz (4 cores),
3,200 MHz (5 cores),
3,100 MHz (6 cores),
3,100 MHz (7 cores),
3,100 MHz (8 cores),
3,100 MHz (9 cores),
3,100 MHz (10 cores),
3,100 MHz (11 cores),
3,100 MHz (12 cores),
3,100 MHz (13 cores),
3,100 MHz (14 cores),
3,100 MHz (15 cores),
3,100 MHz (16 cores)
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier26
CPUID406F1
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingB0
Process14 nm
Transistors7,200,000,000
TechnologyCMOS
Die456.12 mm²
Word Size64 bit
Cores16
Threads32
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP145 W
Tcase0 °C – 78 °C
Tstorage-25 °C – 125 °C

The Xeon E5-2697A v4 is a 64-bit hexadeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for segment-optimized 2S environments (2U Square form factors). Operating at 2.6 GHz with a turbo boost frequency of 3.6 GHz for a single active core, this MPU has a TDP of 145 W and is manufactured on a 14 nm process (based on Broadwell).

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 512 KiB
524,288 B
0.5 MiB
16x32 KiB 8-way set associative (per core, write-back)
L1D$ 512 KiB
524,288 B
0.5 MiB
16x32 KiB 8-way set associative (per core, write-back)
L2$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16x256 KiB 8-way set associative (per core, write-back)
L3$ 40 MiB
40,960 KiB
41,943,040 B
0.0391 GiB
16x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2697a_v4&oldid=102195"
Facts about "Xeon E5-2697A v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-2697A v4 - Intel#io +
base frequency2,600 MHz (2.6 GHz, 2,600,000 kHz) +
bus links2 +
bus rate9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier26 +
core count16 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingB0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area456.12 mm² (0.707 in², 4.561 cm², 456,120,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-2697a v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
isax86-64 +
isa familyx86 +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description8-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description20-way set associative +
l3$ size40 MiB (40,960 KiB, 41,943,040 B, 0.0391 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature351.15 K (78 °C, 172.4 °F, 632.07 °R) +
max cpu count2 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-2697A v4 +
nameXeon E5-2697A v4 +
part numberCM8066002645900 +
platformGrantley EP 2S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 2,891.00 (€ 2,601.90, £ 2,341.71, ¥ 298,727.03) +
s-specSR2K1 +
s-spec (qs)QK7S +
seriesE5-2000 +
smp max ways2 +
tdp145 W (145,000 mW, 0.194 hp, 0.145 kW) +
technologyCMOS +
thread count32 +
transistor count7,200,000,000 +
turbo frequency (10 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (11 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (12 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (13 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (14 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (15 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (16 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (1 core)3,600 MHz (3.6 GHz, 3,600,000 kHz) +
turbo frequency (2 cores)3,600 MHz (3.6 GHz, 3,600,000 kHz) +
turbo frequency (3 cores)3,400 MHz (3.4 GHz, 3,400,000 kHz) +
turbo frequency (4 cores)3,300 MHz (3.3 GHz, 3,300,000 kHz) +
turbo frequency (5 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (6 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (7 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (8 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
turbo frequency (9 cores)3,100 MHz (3.1 GHz, 3,100,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +